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diff --git a/src/openpower/decoder/isa/test_caller_svp64_pospopcount.py b/src/openpower/decoder/isa/test_caller_svp64_pospopcount.py
index d13ea5705d191c215c5f7b58f13b40559dc278a0..efc31ef50444ab5beabde817c134b5dc26021fae 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_pospopcount.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_pospopcount.py
@@ -45,10 +45,10 @@ class PosPopCountTestCase(FHDLTestCase):
                 "sv.lbzu/pi/dw=8 *6, 1(4)", # should be /lf here as well
                 # gather performs the transpose (which gets us to positional..)
                 "gbbd 8,6",
-                # now those bits have been turned around,
+                # now those bits have been turned around, popcount and sum them
                 "setvl 0,0,8,0,1,1",        # set MVL=VL=8
                 "sv.popcntd/sw=8 *24,*8",   # do the (now transposed) popcount
-                "sv.add *16,*16,*24",
+                "sv.add *16,*16,*24",       # and accumulate in results
                 # branch back if still CTR
                 "sv.bc/all 16, *0, -0x28", # CTR mode, reduce VL by CTR
             ]