so->inputs[n].compmask = (1 << (ncomp + frac)) - 1;
so->inputs_count = MAX2(so->inputs_count, n + 1);
so->inputs[n].interpolate = in->data.interpolation;
- so->inputs[n].ncomp = ncomp;
if (ctx->so->type == MESA_SHADER_FRAGMENT) {
for (unsigned i = 0; i < so->inputs_count; i++) {
unsigned compmask = 0, maxcomp = 0;
- so->inputs[i].ncomp = 0;
so->inputs[i].inloc = inloc;
so->inputs[i].bary = false;
compmask |= (1 << j);
actual_in++;
- so->inputs[i].ncomp++;
maxcomp = j + 1;
/* at this point, since used_components[i] mask is only
uint8_t slot;
uint8_t regid;
uint8_t compmask;
- uint8_t ncomp;
/* location of input (ie. offset passed to bary.f, etc). This
* matches the SP_VS_VPC_DST_REG.OUTLOCn value (a3xx and a4xx
* have the OUTLOCn value offset by 8, presumably to account
COND(isint, A3XX_VFD_DECODE_INSTR_INT) |
COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
- total_in += vp->inputs[i].ncomp;
+ total_in += util_bitcount(vp->inputs[i].compmask);
j++;
}
}
COND(isint, A4XX_VFD_DECODE_INSTR_INT) |
COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
- total_in += vp->inputs[i].ncomp;
+ total_in += util_bitcount(vp->inputs[i].compmask);
j++;
}
}