projects
/
yosys.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
fdfc18b
)
Do not double count LUT1s
author
Eddie Hung
<eddie@fpgeh.com>
Thu, 30 May 2019 18:32:14 +0000
(11:32 -0700)
committer
Eddie Hung
<eddie@fpgeh.com>
Thu, 30 May 2019 18:32:14 +0000
(11:32 -0700)
passes/techmap/abc9.cc
patch
|
blob
|
history
diff --git
a/passes/techmap/abc9.cc
b/passes/techmap/abc9.cc
index 8966b5c279f8a3a79d00e9b4aeb6b9b8890894f4..b1bd167a4a8f7e03e714483873f8447b69172744 100644
(file)
--- a/
passes/techmap/abc9.cc
+++ b/
passes/techmap/abc9.cc
@@
-670,7
+670,6
@@
void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset),
driver_lut);
}
- cell_stats["$lut"]++;
}
else {
cell = module->addCell(remap_name(c->name), "$_NOT_");