fhdl/verilog: fix signedness rules for comparison

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index 8dc404fe07986b6be27c88a3481daae9af850a5b..d9683e9404185aa987d6afd8d9e014d77f01b0c2 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -51,7 +51,7 @@ def _printexpr(ns, node):
                                s = s1
                elif arity == 2:
                        r2, s2 = _printexpr(ns, node.operands[1])
-                       if node.op in ["+", "-", "*", "&", "^", "|"]:
+                       if node.op not in ["<<<", ">>>"]:
                                if s2 and not s1:
                                        r1 = "$signed({1'd0, " + r1 + "})"
                                if s1 and not s2: