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diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 2d5b639f684a9be479fc2f6496c35e385aec275f..6a4b3e1944f576185b216d36a5f55e5151683422 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -497,35 +497,6 @@ When Rc=1 a corresponding Vector of co-resultant CRs is also
 created.  No special action is taken: the result and its CR Field
 are stored "as usual" exactly as all other SVP64 Rc=1 operations.
 
-## Sub-Vector Horizontal Reduction
-
-Note that when SVM is clear and SUBVL!=1 the sub-elements are
-*independent*, i.e. they are mapreduced per *sub-element* as a result.
-illustration with a vec2, assuming RA==RT, e.g `sv.add/mr/vec2 r4, r4, r16`
-
-    for i in range(0, VL):
-        # RA==RT in the instruction. does not have to be
-        iregs[RT].x = op(iregs[RT].x, iregs[RB+i].x)
-        iregs[RT].y = op(iregs[RT].y, iregs[RB+i].y)
-
-Thus logically there is nothing special or unanticipated about
-`SVM=0`: it is expected behaviour according to standard SVP64
-Sub-Vector rules.
-
-By contrast, when SVM is set and SUBVL!=1, a Horizontal
-Subvector mode is enabled, which behaves very much more
-like a traditional Vector Processor Reduction instruction.
-Example for a vec3:
-
-    for i in range(VL):
-        result = iregs[RA+i].x
-        result = op(result, iregs[RA+i].y)
-        result = op(result, iregs[RA+i].z)
-        iregs[RT+i] = result
-
-In this mode, when Rc=1 the Vector of CRs is as normal: each result
-element creates a corresponding CR element (for the final, reduced, result).
-
 # Fail-on-first
 
 Data-dependent fail-on-first has two distinct variants: one for LD/ST
@@ -975,13 +946,13 @@ limit the Reduction Sequence for all implementors
 based solely and exclusively on what one
 specific internal microarchitecture does.
 In SIMD ISAs the internal SIMD Architectural design is exposed and imposed on the programmer. Cray-style Vector ISAs on the other hand provide convenient,
-compact and efficient encodings of abstract concepts.
-It is the Implementor's responsibility to produce a design
+compact and efficient encodings of abstract concepts.*
+**It is the Implementor's responsibility to produce a design
 that complies with the above algorithm,
 utilising internal Micro-coding and other techniques to transparently
-insert MV operations
+insert micro-architectural lane-crossing Move operations
 if necessary or desired, to give the level of efficiency or performance
-required.*
+required.**
 
 # Element-width overrides <a name="elwidth"> </>