renumber VCC/VSS, move PLL around

diff --git a/180nm_Oct2020/ls180.mdwn b/180nm_Oct2020/ls180.mdwn
index 7eec295d1c8e112109892b9c49ae7a758641b833..10e3faaf41d2caddc32ce4869788aa43c67d5e72 100644 (file)
--- a/180nm_Oct2020/ls180.mdwn
+++ b/180nm_Oct2020/ls180.mdwn
@@ -8,33 +8,33 @@ auto-generated by [[pinouts.py]]
 
 | Pin | Mux0        | Mux1        | Mux2        | Mux3        |
 | --- | ----------- | ----------- | ----------- | ----------- |
-|   0 | N VSSE_2    |             |
-|   1 | N VDDE_2    |             |
-|   2 | N VDDI_12   |             |
-|   3 | N VSSI_12   |             |
-|  22 | N SYS_PLLCLK |             |
-|  23 | N SYS_PLLSELA0 |             |
-|  24 | N SYS_PLLSELA1 |             |
-|  25 | N SYS_PLLTESTOUT |             |
-|  26 | N SYS_PLLVCOUT |             |
-|  27 | N SYS_RST   |             |
-|  28 | N VSSI_11   |             |
-|  29 | N VDDI_11   |             |
-|  30 | N VSSI_4    |             |
-|  31 | N VDDI_4    |             |
+|   0 | N VSSE_6    |             |
+|   1 | N VDDE_6    |             |
+|   2 | N VDDI_6    |             |
+|   3 | N VSSI_6    |             |
+|  23 | N SYS_RST   |             |
+|  24 | N SYS_PLLSELA0 |             |
+|  25 | N SYS_PLLSELA1 |             |
+|  26 | N SYS_PLLCLK |             |
+|  27 | N SYS_PLLTESTOUT |             |
+|  28 | N VSSI_7    |             |
+|  29 | N VDDI_7    |             |
+|  30 | N VSSI_7    |             |
+|  31 | N VDDI_7    |             |
 
 ## Bank E (32 pins, width 2)
 
 | Pin | Mux0        | Mux1        | Mux2        | Mux3        |
 | --- | ----------- | ----------- | ----------- | ----------- |
-|  32 | E VSSI_2    |             |
-|  33 | E VDDI_2    |             |
-|  34 | E VDDI_10   |             |
-|  35 | E VSSI_10   |             |
-|  36 | E MSPI0_CK  |             |
-|  37 | E MSPI0_NSS |             |
-|  38 | E MSPI0_MOSI |             |
-|  39 | E MSPI0_MISO |             |
+|  32 | E VSSI_4    |             |
+|  33 | E VDDI_4    |             |
+|  34 | E VDDI_4    |             |
+|  35 | E VSSI_4    |             |
+|  36 | E SYS_PLLVCOUT |             |
+|  37 | E MSPI0_CK  |             |
+|  38 | E MSPI0_NSS |             |
+|  39 | E MSPI0_MOSI |             |
+|  40 | E MSPI0_MISO |             |
 |  41 | E GPIOE_E0  |             |
 |  42 | E GPIOE_E1  |             |
 |  43 | E GPIOE_E2  |             |
@@ -54,10 +54,10 @@ auto-generated by [[pinouts.py]]
 |  57 | E EINT_0    |             |
 |  58 | E EINT_1    |             |
 |  59 | E EINT_2    |             |
-|  60 | E VSSI_9    |             |
-|  61 | E VDDI_9    |             |
-|  62 | E VSSI_3    |             |
-|  63 | E VDDI_3    |             |
+|  60 | E VSSI_5    |             |
+|  61 | E VDDI_5    |             |
+|  62 | E VSSI_5    |             |
+|  63 | E VDDI_5    |             |
 
 ## Bank S (32 pins, width 2)
 
@@ -65,8 +65,8 @@ auto-generated by [[pinouts.py]]
 | --- | ----------- | ----------- | ----------- | ----------- |
 |  64 | S VDDE_0    |             |
 |  65 | S VSSE_0    |             |
-|  66 | S VDDI_5    |             |
-|  67 | S VSSI_5    |             |
+|  66 | S VDDI_0    |             |
+|  67 | S VSSI_0    |             |
 |  68 | S SDR_DQM0  |             |
 |  69 | S SDR_D0    |             |
 |  70 | S SDR_D1    |             |
@@ -90,19 +90,19 @@ auto-generated by [[pinouts.py]]
 |  88 | S SDR_BA1   |             |
 |  90 | S MTWI_SDA  |             |
 |  91 | S MTWI_SCL  |             |
-|  92 | S VSSI_6    |             |
-|  93 | S VDDI_6    |             |
-|  94 | S VSSE_13   |             |
-|  95 | S VDDE_13   |             |
+|  92 | S VSSI_1    |             |
+|  93 | S VDDI_1    |             |
+|  94 | S VSSE_1    |             |
+|  95 | S VDDE_1    |             |
 
 ## Bank W (32 pins, width 2)
 
 | Pin | Mux0        | Mux1        | Mux2        | Mux3        |
 | --- | ----------- | ----------- | ----------- | ----------- |
-|  96 | W VDDE_1    |             |
-|  97 | W VSSE_1    |             |
-|  98 | W VDDI_7    |             |
-|  99 | W VSSI_7    |             |
+|  96 | W VDDE_2    |             |
+|  97 | W VSSE_2    |             |
+|  98 | W VDDI_2    |             |
+|  99 | W VSSI_2    |             |
 | 100 | W SDR_AD10  |             |
 | 101 | W SDR_AD11  |             |
 | 102 | W SDR_AD12  |             |
@@ -127,10 +127,10 @@ auto-generated by [[pinouts.py]]
 | 121 | W JTAG_TDI  |             |
 | 122 | W JTAG_TDO  |             |
 | 123 | W JTAG_TCK  |             |
-| 124 | W VSSI_14   |             |
-| 125 | W VDDI_14   |             |
-| 126 | W VSSE_8    |             |
-| 127 | W VDDE_8    |             |
+| 124 | W VSSI_3    |             |
+| 125 | W VDDI_3    |             |
+| 126 | W VSSE_3    |             |
+| 127 | W VDDE_3    |             |
 
 # Pinouts (Fixed function)
 
@@ -180,10 +180,10 @@ JTAG
 
 SPI Master 1 (general)
 
-* MSPI0_CK  : E4/0
-* MSPI0_MISO : E7/0
-* MSPI0_MOSI : E6/0
-* MSPI0_NSS : E5/0
+* MSPI0_CK  : E5/0
+* MSPI0_MISO : E8/0
+* MSPI0_MOSI : E7/0
+* MSPI0_NSS : E6/0
 
 ## MTWI
 
@@ -240,12 +240,12 @@ SDRAM
 
 System Control
 
-* SYS_PLLCLK : N22/0
-* SYS_PLLSELA0 : N23/0
-* SYS_PLLSELA1 : N24/0
-* SYS_PLLTESTOUT : N25/0
-* SYS_PLLVCOUT : N26/0
-* SYS_RST   : N27/0
+* SYS_PLLCLK : N26/0
+* SYS_PLLSELA0 : N24/0
+* SYS_PLLSELA1 : N25/0
+* SYS_PLLTESTOUT : N27/0
+* SYS_PLLVCOUT : E4/0
+* SYS_RST   : N23/0
 
 ## UART0
 
@@ -259,42 +259,36 @@ UART (TX/RX) 1
 Power
 
 * VDDE_0    : S0/0
-* VDDE_1    : W0/0
-* VDDE_2    : N1/0
-* VDDE_8    : W31/0
-* VDDE_13   : S31/0
-* VDDI_2    : E1/0
-* VDDI_3    : E31/0
-* VDDI_4    : N31/0
-* VDDI_5    : S2/0
-* VDDI_6    : S29/0
-* VDDI_7    : W2/0
-* VDDI_9    : E29/0
-* VDDI_10   : E2/0
-* VDDI_11   : N29/0
-* VDDI_12   : N2/0
-* VDDI_14   : W29/0
+* VDDE_1    : S31/0
+* VDDE_2    : W0/0
+* VDDE_3    : W31/0
+* VDDE_6    : N1/0
+* VDDI_0    : S2/0
+* VDDI_1    : S29/0
+* VDDI_2    : W2/0
+* VDDI_3    : W29/0
+* VDDI_4    : E1/0 E2/0
+* VDDI_5    : E29/0 E31/0
+* VDDI_6    : N2/0
+* VDDI_7    : N29/0 N31/0
 
 ## VSS
 
 GND
 
 * VSSE_0    : S1/0
-* VSSE_1    : W1/0
-* VSSE_2    : N0/0
-* VSSE_8    : W30/0
-* VSSE_13   : S30/0
-* VSSI_2    : E0/0
-* VSSI_3    : E30/0
-* VSSI_4    : N30/0
-* VSSI_5    : S3/0
-* VSSI_6    : S28/0
-* VSSI_7    : W3/0
-* VSSI_9    : E28/0
-* VSSI_10   : E3/0
-* VSSI_11   : N28/0
-* VSSI_12   : N3/0
-* VSSI_14   : W28/0
+* VSSE_1    : S30/0
+* VSSE_2    : W1/0
+* VSSE_3    : W30/0
+* VSSE_6    : N0/0
+* VSSI_0    : S3/0
+* VSSI_1    : S28/0
+* VSSI_2    : W3/0
+* VSSI_3    : W28/0
+* VSSI_4    : E0/0 E3/0
+* VSSI_5    : E28/0 E30/0
+* VSSI_6    : N3/0
+* VSSI_7    : N28/0 N30/0
 
 # Pinmap for Libre-SOC 180nm
 
@@ -345,30 +339,30 @@ GND
 
 ## VDD
 
-* VDDE_2 1 N1/0
-* VDDI_12 2 N2/0
-* VDDI_11 29 N29/0
-* VDDI_4 31 N31/0
-* VDDI_2 33 E1/0
+* VDDE_6 1 N1/0
+* VDDI_6 2 N2/0
+* VDDI_7 29 N29/0
+* VDDI_4 33 E1/0
+* VDDI_5 61 E29/0
 
 ## VSS
 
-* VSSE_2 0 N0/0
-* VSSI_12 3 N3/0
-* VSSI_11 28 N28/0
-* VSSI_4 30 N30/0
-* VSSI_2 32 E0/0
+* VSSE_6 0 N0/0
+* VSSI_6 3 N3/0
+* VSSI_7 28 N28/0
+* VSSI_4 32 E0/0
+* VSSI_5 60 E28/0
 
 ## SYS
 
 
 
-* SYS_PLLCLK 22 N22/0
-* SYS_PLLSELA0 23 N23/0
-* SYS_PLLSELA1 24 N24/0
-* SYS_PLLTESTOUT 25 N25/0
-* SYS_PLLVCOUT 26 N26/0
-* SYS_RST 27 N27/0
+* SYS_RST 23 N23/0
+* SYS_PLLSELA0 24 N24/0
+* SYS_PLLSELA1 25 N25/0
+* SYS_PLLCLK 26 N26/0
+* SYS_PLLTESTOUT 27 N27/0
+* SYS_PLLVCOUT 36 E4/0
 
 ## MTWI
 
@@ -380,10 +374,10 @@ I2C.
 
 ## MSPI0
 
-* MSPI0_CK 36 E4/0
-* MSPI0_NSS 37 E5/0
-* MSPI0_MOSI 38 E6/0
-* MSPI0_MISO 39 E7/0
+* MSPI0_CK 37 E5/0
+* MSPI0_NSS 38 E6/0
+* MSPI0_MOSI 39 E7/0
+* MSPI0_MISO 40 E8/0
 
 ## SDR
 
@@ -433,28 +427,28 @@ I2C.
 
 | Pin | Mux0        | Mux1        | Mux2        | Mux3        |
 | --- | ----------- | ----------- | ----------- | ----------- |
-|  34 | E VDDI_10   |             |             |             |
-|  35 | E VSSI_10   |             |             |             |
-|  60 | E VSSI_9    |             |             |             |
-|  61 | E VDDI_9    |             |             |             |
-|  62 | E VSSI_3    |             |             |             |
-|  63 | E VDDI_3    |             |             |             |
+|  30 | N VSSI_7    |             |             |             |
+|  31 | N VDDI_7    |             |             |             |
+|  34 | E VDDI_4    |             |             |             |
+|  35 | E VSSI_4    |             |             |             |
+|  62 | E VSSI_5    |             |             |             |
+|  63 | E VDDI_5    |             |             |             |
 |  64 | S VDDE_0    |             |             |             |
 |  65 | S VSSE_0    |             |             |             |
-|  66 | S VDDI_5    |             |             |             |
-|  67 | S VSSI_5    |             |             |             |
-|  92 | S VSSI_6    |             |             |             |
-|  93 | S VDDI_6    |             |             |             |
-|  94 | S VSSE_13   |             |             |             |
-|  95 | S VDDE_13   |             |             |             |
-|  96 | W VDDE_1    |             |             |             |
-|  97 | W VSSE_1    |             |             |             |
-|  98 | W VDDI_7    |             |             |             |
-|  99 | W VSSI_7    |             |             |             |
-| 124 | W VSSI_14   |             |             |             |
-| 125 | W VDDI_14   |             |             |             |
-| 126 | W VSSE_8    |             |             |             |
-| 127 | W VDDE_8    |             |             |             |
+|  66 | S VDDI_0    |             |             |             |
+|  67 | S VSSI_0    |             |             |             |
+|  92 | S VSSI_1    |             |             |             |
+|  93 | S VDDI_1    |             |             |             |
+|  94 | S VSSE_1    |             |             |             |
+|  95 | S VDDE_1    |             |             |             |
+|  96 | W VDDE_2    |             |             |             |
+|  97 | W VSSE_2    |             |             |             |
+|  98 | W VDDI_2    |             |             |             |
+|  99 | W VSSI_2    |             |             |             |
+| 124 | W VSSI_3    |             |             |             |
+| 125 | W VDDI_3    |             |             |             |
+| 126 | W VSSE_3    |             |             |             |
+| 127 | W VDDE_3    |             |             |             |
 
 # Reference Datasheets