etherbone: probing OK on hardware

diff --git a/test/Makefile b/test/Makefile
new file mode 100644 (file)
index 0000000..0556486
--- /dev/null
+++ b/test/Makefile
@@ -0,0 +1,16 @@
+LEDIR = ../
+PYTHON = python3
+
+CMD = PYTHONPATH=$(LEDIR) $(PYTHON)
+
+test_regs:
+       $(CMD) test_regs.py
+
+test_la:
+       $(CMD) test_la.py
+
+test_udp:
+       $(CMD) test_udp.py
+
+test_etherbone:
+       $(CMD) test_etherbone.py

diff --git a/test/test_etherbone.py b/test/test_etherbone.py
new file mode 100644 (file)
index 0000000..e11773b
--- /dev/null
+++ b/test/test_etherbone.py
@@ -0,0 +1,13 @@
+import socket
+from liteeth.test.model.etherbone import *
+
+SRAM_BASE = 0x02000000
+
+import socket
+sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
+
+# test probe
+packet = EtherbonePacket()
+packet.pf = 1
+packet.encode()
+sock.sendto(bytes(packet), ("192.168.1.40", 20000))

diff --git a/test/test_la.py b/test/test_la.py
index e73f3713b68637cd39157e37a493ed49b57e04c3..8bf205feafe95b2c4b0d1209c5cecc059401306a 100644 (file)
--- a/test/test_la.py
+++ b/test/test_la.py
@@ -15,6 +15,9 @@ conditions = {
 conditions = {
        "core_udp_tx_fsm_state" : 1
 }
+conditions = {
+       "etherbonesocdevel_master_bus_stb"      : 1
+}
 la.configure_term(port=0, cond=conditions)
 la.configure_sum("term")
 # Run Logic Analyzer