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diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index ffa1b2e95ddc5959eaac26aa425c4e47d63f644f..e5e077015ff104bf8f5ab3a5c64f1489474210ae 100644 (file)
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -185,8 +185,9 @@ Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or in
 # Mode
 
 Mode is an augmentation of SV behaviour.  Different types of
-instructions have different needs, similar to Power ISA 64 bit prefix
-8LS and MTRR formats.
+instructions have different needs, similar to Power ISA 
+v3.1 64 bit prefix 8LS and MTRR formats apply to different
+instruction types
 
 * For condition register operations see [[sv/cr_ops]]
 * For LD/ST Modes, see [[sv/ldst]].