Towards Xilinx bram support

diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc
index e7a42f26d50051dec20bda4405237f6445a3d6af..fd5db188eb0439e2995ef2fef6d81ad1f896a2c8 100644 (file)
--- a/passes/memory/memory_bram.cc
+++ b/passes/memory/memory_bram.cc
@@ -356,7 +356,7 @@ bool replace_cell(Cell *cell, const rules_t::bram_t &bram, const rules_t::match_
                        for (int i = 0; i < fillbits; i++) {
                                for (int j = 0; j < wr_ports; j++) {
                                        new_wr_en[j].append(fillbit);
-                                       new_wr_data[j].append(State::Sx);
+                                       new_wr_data[j].append(State::S0);
                                }
                                for (int j = 0; j < rd_ports; j++)
                                        new_rd_data[j].append(State::Sx);

diff --git a/techlibs/xilinx/brams.v b/techlibs/xilinx/brams.v
index 49219c8a14eeaa015113a586bfae92e23fb1ad8e..f98625bfaf13f4d3a800a2fb57e4723f53b377aa 100644 (file)
--- a/techlibs/xilinx/brams.v
+++ b/techlibs/xilinx/brams.v
@@ -19,8 +19,29 @@ module \$__XILINX_RAMB36_SDP72 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
        wire [7:0] DIP, DOP;
        wire [63:0] DI, DO;
 
-       assign A1DATA = { DOP[7], DO[63:56], DOP[6], DO[55:48], DOP[5], DO[47:40], DOP[4], DO[39:32],
-                         DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
+       wire [71:0] A1DATA_BUF;
+       reg [71:0] B1DATA_Q;
+       reg [7:0] transparent_cycle;
+
+       wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
+
+       generate if (CLKPOL2)
+               always @(posedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
+       else
+               always @(negedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
+       endgenerate
+
+       assign A1DATA[ 8: 0] = transparent_cycle[0] ? B1DATA_Q[ 8: 0] : A1DATA_BUF[ 8: 0];
+       assign A1DATA[17: 9] = transparent_cycle[1] ? B1DATA_Q[17: 9] : A1DATA_BUF[17: 9];
+       assign A1DATA[26:18] = transparent_cycle[2] ? B1DATA_Q[26:18] : A1DATA_BUF[26:18];
+       assign A1DATA[35:27] = transparent_cycle[3] ? B1DATA_Q[35:27] : A1DATA_BUF[35:27];
+       assign A1DATA[44:36] = transparent_cycle[4] ? B1DATA_Q[44:36] : A1DATA_BUF[44:36];
+       assign A1DATA[53:45] = transparent_cycle[5] ? B1DATA_Q[53:45] : A1DATA_BUF[53:45];
+       assign A1DATA[62:54] = transparent_cycle[6] ? B1DATA_Q[62:54] : A1DATA_BUF[62:54];
+       assign A1DATA[71:63] = transparent_cycle[7] ? B1DATA_Q[71:63] : A1DATA_BUF[71:63];
+
+       assign A1DATA_BUF = { DOP[7], DO[63:56], DOP[6], DO[55:48], DOP[5], DO[47:40], DOP[4], DO[39:32],
+                             DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
 
        assign { DIP[7], DI[63:56], DIP[6], DI[55:48], DIP[5], DI[47:40], DIP[4], DI[39:32],
                 DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;

diff --git a/techlibs/xilinx/tests/bram1.sh b/techlibs/xilinx/tests/bram1.sh
index fe807ad8f78c7aefcdc5d55c0228272ba7957198..f233be9faa3cf928584c569833bda444e07af1f7 100644 (file)
--- a/techlibs/xilinx/tests/bram1.sh
+++ b/techlibs/xilinx/tests/bram1.sh
@@ -1,13 +1,15 @@
 #!/bin/bash
 
+use_xsim=false
+unisims=/opt/Xilinx/Vivado/2014.4/data/verilog/src/unisims
+
 echo "all: all_list" > bram1.mk
-all_list="all_list:"
+all_list=""
 
 for transp in 0 1; do
 for abits in 1 2 4 8 10 16 20; do
 for dbits in 1 2 4 8 10 16 20 24 30 32 40 48 50 56 60 64 70 72 80; do
        if [ $(( (1 << $abits) * $dbits )) -gt 1000000 ]; then continue; fi
-       if [ $(( (1 << $abits) * $dbits )) -gt 100 ]; then continue; fi
        id=`printf "%d%02d%02d" $transp $abits $dbits`
        echo "Creating bram1_$id.."
        rm -rf bram1_$id
@@ -19,12 +21,17 @@ for dbits in 1 2 4 8 10 16 20 24 30 32 40 48 50 56 60 64 70 72 80; do
        {
                echo "set -e"
                echo "../../../../yosys -q -lsynth.log -p 'synth_xilinx -top bram1; write_verilog synth.v' bram1.v"
-               echo "xvlog --work gold bram1_tb.v bram1.v > gold.txt"
-               echo "xvlog --work gate bram1_tb.v synth.v > gate.txt"
-               echo "xelab -R gold.bram1_tb >> gold.txt"
-               # echo "mv testbench.vcd gold.vcd"
-               echo "xelab -L unisim -R gate.bram1_tb >> gate.txt"
-               # echo "mv testbench.vcd gate.vcd"
+               if $use_xsim; then
+                       echo "xvlog --work gold bram1_tb.v bram1.v > gold.txt"
+                       echo "xvlog --work gate bram1_tb.v synth.v > gate.txt"
+                       echo "xelab -R gold.bram1_tb >> gold.txt"
+                       echo "xelab -L unisim -R gate.bram1_tb >> gate.txt"
+               else
+                       echo "iverilog -o bram1_tb_gold bram1_tb.v bram1.v > gold.txt 2>&1"
+                       echo "iverilog -o bram1_tb_gate bram1_tb.v synth.v -y $unisims $unisims/../glbl.v > gate.txt 2>&1"
+                       echo "./bram1_tb_gold >> gold.txt"
+                       echo "./bram1_tb_gate >> gate.txt"
+               fi
                echo "../bram1_cmp <( grep '#OUT#' gold.txt; ) <( grep '#OUT#' gate.txt; )"
        } > bram1_$id/run.sh
        {
@@ -37,12 +44,12 @@ for dbits in 1 2 4 8 10 16 20 24 30 32 40 48 50 56 60 64 70 72 80; do
 done; done; done
 
 cc -o bram1_cmp ../../../tests/tools/cmp_tbdata.c
-echo "$all_list" >> bram1.mk
+echo all_list: $(echo $all_list | tr ' ' '\n' | sort -R) >> bram1.mk
 
 echo "Testing..."
 ${MAKE:-make} -f bram1.mk
 echo
 
-# echo "Cleaning up..."
-# rm -rf bram1_cmp bram1.mk bram1_[0-9]*/
+echo "Cleaning up..."
+rm -rf bram1_cmp bram1.mk bram1_[0-9]*/