return nr_bytes;
}
-/* XXX: This doesn't handle DMA<->peripheral mappings. */
+/* Give each SIC its own base to make it easier to extract the pin at
+ runtime. The pin is used as its bit position in the SIC MMRs. */
+#define ENC(sic, pin) (((sic) << 8) + (pin))
+#define DEC_PIN(pin) ((pin) % 0x100)
+#define DEC_SIC(pin) ((pin) >> 8)
+
+/* It would be nice to declare just one set of input_ports, and then
+ have the device tree instantiate multiple SICs, but the MMR layout
+ on the BF54x/BF561 makes this pretty hard to pull off since their
+ regs are interwoven in the address space. */
+
#define BFIN_SIC_TO_CEC_PORTS \
{ "ivg7", IVG7, 0, output_port, }, \
{ "ivg8", IVG8, 0, output_port, }, \
{ "ivg14", IVG14, 0, output_port, }, \
{ "ivg15", IVG15, 0, output_port, },
-/* Give each SIC its own base to make it easier to extract the pin at
- runtime. The pin is used as its bit position in the SIC MMRs. */
-#define ENC(sic, pin) (((sic) << 8) + (pin))
-#define DEC_PIN(pin) ((pin) % 0x100)
-#define DEC_SIC(pin) ((pin) >> 8)
+#define SIC_PORTS(n) \
+ { "int0@"#n, ENC(n, 0), 0, input_port, }, \
+ { "int1@"#n, ENC(n, 1), 0, input_port, }, \
+ { "int2@"#n, ENC(n, 2), 0, input_port, }, \
+ { "int3@"#n, ENC(n, 3), 0, input_port, }, \
+ { "int4@"#n, ENC(n, 4), 0, input_port, }, \
+ { "int5@"#n, ENC(n, 5), 0, input_port, }, \
+ { "int6@"#n, ENC(n, 6), 0, input_port, }, \
+ { "int7@"#n, ENC(n, 7), 0, input_port, }, \
+ { "int8@"#n, ENC(n, 8), 0, input_port, }, \
+ { "int9@"#n, ENC(n, 9), 0, input_port, }, \
+ { "int10@"#n, ENC(n, 10), 0, input_port, }, \
+ { "int11@"#n, ENC(n, 11), 0, input_port, }, \
+ { "int12@"#n, ENC(n, 12), 0, input_port, }, \
+ { "int13@"#n, ENC(n, 13), 0, input_port, }, \
+ { "int14@"#n, ENC(n, 14), 0, input_port, }, \
+ { "int15@"#n, ENC(n, 15), 0, input_port, }, \
+ { "int16@"#n, ENC(n, 16), 0, input_port, }, \
+ { "int17@"#n, ENC(n, 17), 0, input_port, }, \
+ { "int18@"#n, ENC(n, 18), 0, input_port, }, \
+ { "int19@"#n, ENC(n, 19), 0, input_port, }, \
+ { "int20@"#n, ENC(n, 20), 0, input_port, }, \
+ { "int21@"#n, ENC(n, 21), 0, input_port, }, \
+ { "int22@"#n, ENC(n, 22), 0, input_port, }, \
+ { "int23@"#n, ENC(n, 23), 0, input_port, }, \
+ { "int24@"#n, ENC(n, 24), 0, input_port, }, \
+ { "int25@"#n, ENC(n, 25), 0, input_port, }, \
+ { "int26@"#n, ENC(n, 26), 0, input_port, }, \
+ { "int27@"#n, ENC(n, 27), 0, input_port, }, \
+ { "int28@"#n, ENC(n, 28), 0, input_port, }, \
+ { "int29@"#n, ENC(n, 29), 0, input_port, }, \
+ { "int30@"#n, ENC(n, 30), 0, input_port, }, \
+ { "int31@"#n, ENC(n, 31), 0, input_port, },
+
+static const struct hw_port_descriptor bfin_sic1_ports[] =
+{
+ BFIN_SIC_TO_CEC_PORTS
+ SIC_PORTS(0)
+ { NULL, 0, 0, 0, },
+};
-static const struct hw_port_descriptor bfin_sic_50x_ports[] =
+static const struct hw_port_descriptor bfin_sic2_ports[] =
{
BFIN_SIC_TO_CEC_PORTS
- /* SIC0 */
- { "pll", ENC(0, 0), 0, input_port, },
- { "dma_stat", ENC(0, 1), 0, input_port, },
- { "ppi@0", ENC(0, 2), 0, input_port, },
- { "sport@0_stat", ENC(0, 3), 0, input_port, },
- { "sport@1_stat", ENC(0, 4), 0, input_port, },
- { "uart2@0_stat", ENC(0, 5), 0, input_port, },
- { "uart2@1_stat", ENC(0, 6), 0, input_port, },
- { "spi@0", ENC(0, 7), 0, input_port, },
- { "spi@1", ENC(0, 8), 0, input_port, },
- { "can_stat", ENC(0, 9), 0, input_port, },
- { "rsi_int0", ENC(0, 10), 0, input_port, },
-/*{ "reserved", ENC(0, 11), 0, input_port, },*/
- { "counter@0", ENC(0, 12), 0, input_port, },
- { "counter@1", ENC(0, 13), 0, input_port, },
- { "dma@0", ENC(0, 14), 0, input_port, },
- { "dma@1", ENC(0, 15), 0, input_port, },
- { "dma@2", ENC(0, 16), 0, input_port, },
- { "dma@3", ENC(0, 17), 0, input_port, },
- { "dma@4", ENC(0, 18), 0, input_port, },
- { "dma@5", ENC(0, 19), 0, input_port, },
- { "dma@6", ENC(0, 20), 0, input_port, },
- { "dma@7", ENC(0, 21), 0, input_port, },
- { "dma@8", ENC(0, 22), 0, input_port, },
- { "dma@9", ENC(0, 23), 0, input_port, },
- { "dma@10", ENC(0, 24), 0, input_port, },
- { "dma@11", ENC(0, 25), 0, input_port, },
- { "can_rx", ENC(0, 26), 0, input_port, },
- { "can_tx", ENC(0, 27), 0, input_port, },
- { "twi@0", ENC(0, 28), 0, input_port, },
- { "portf_irq_a", ENC(0, 29), 0, input_port, },
- { "portf_irq_b", ENC(0, 30), 0, input_port, },
-/*{ "reserved", ENC(0, 31), 0, input_port, },*/
- /* SIC1 */
- { "gptimer@0", ENC(1, 0), 0, input_port, },
- { "gptimer@1", ENC(1, 1), 0, input_port, },
- { "gptimer@2", ENC(1, 2), 0, input_port, },
- { "gptimer@3", ENC(1, 3), 0, input_port, },
- { "gptimer@4", ENC(1, 4), 0, input_port, },
- { "gptimer@5", ENC(1, 5), 0, input_port, },
- { "gptimer@6", ENC(1, 6), 0, input_port, },
- { "gptimer@7", ENC(1, 7), 0, input_port, },
- { "portg_irq_a", ENC(1, 8), 0, input_port, },
- { "portg_irq_b", ENC(1, 9), 0, input_port, },
- { "mdma@0", ENC(1, 10), 0, input_port, },
- { "mdma@1", ENC(1, 11), 0, input_port, },
- { "wdog", ENC(1, 12), 0, input_port, },
- { "porth_irq_a", ENC(1, 13), 0, input_port, },
- { "porth_irq_b", ENC(1, 14), 0, input_port, },
- { "acm_stat", ENC(1, 15), 0, input_port, },
- { "acm_int", ENC(1, 16), 0, input_port, },
-/*{ "reserved", ENC(1, 17), 0, input_port, },*/
-/*{ "reserved", ENC(1, 18), 0, input_port, },*/
- { "pwm@0_trip", ENC(1, 19), 0, input_port, },
- { "pwm@0_sync", ENC(1, 20), 0, input_port, },
- { "pwm@1_trip", ENC(1, 21), 0, input_port, },
- { "pwm@1_sync", ENC(1, 22), 0, input_port, },
- { "rsi_int1", ENC(1, 23), 0, input_port, },
+ SIC_PORTS(0)
+ SIC_PORTS(1)
{ NULL, 0, 0, 0, },
};
-static const struct hw_port_descriptor bfin_sic_51x_ports[] =
+static const struct hw_port_descriptor bfin_sic3_ports[] =
{
BFIN_SIC_TO_CEC_PORTS
- /* SIC0 */
- { "pll", ENC(0, 0), 0, input_port, },
- { "dma_stat", ENC(0, 1), 0, input_port, },
- { "dmar0_block", ENC(0, 2), 0, input_port, },
- { "dmar1_block", ENC(0, 3), 0, input_port, },
- { "dmar0_over", ENC(0, 4), 0, input_port, },
- { "dmar1_over", ENC(0, 5), 0, input_port, },
- { "ppi@0", ENC(0, 6), 0, input_port, },
- { "emac_stat", ENC(0, 7), 0, input_port, },
- { "sport@0_stat", ENC(0, 8), 0, input_port, },
- { "sport@1_stat", ENC(0, 9), 0, input_port, },
- { "ptp_err", ENC(0, 10), 0, input_port, },
-/*{ "reserved", ENC(0, 11), 0, input_port, },*/
- { "uart@0_stat", ENC(0, 12), 0, input_port, },
- { "uart@1_stat", ENC(0, 13), 0, input_port, },
- { "rtc", ENC(0, 14), 0, input_port, },
- { "dma@0", ENC(0, 15), 0, input_port, },
- { "dma@3", ENC(0, 16), 0, input_port, },
- { "dma@4", ENC(0, 17), 0, input_port, },
- { "dma@5", ENC(0, 18), 0, input_port, },
- { "dma@6", ENC(0, 19), 0, input_port, },
- { "twi@0", ENC(0, 20), 0, input_port, },
- { "dma@7", ENC(0, 21), 0, input_port, },
- { "dma@8", ENC(0, 22), 0, input_port, },
- { "dma@9", ENC(0, 23), 0, input_port, },
- { "dma@10", ENC(0, 24), 0, input_port, },
- { "dma@11", ENC(0, 25), 0, input_port, },
- { "otp", ENC(0, 26), 0, input_port, },
- { "counter", ENC(0, 27), 0, input_port, },
- { "dma@1", ENC(0, 28), 0, input_port, },
- { "porth_irq_a", ENC(0, 29), 0, input_port, },
- { "dma@2", ENC(0, 30), 0, input_port, },
- { "porth_irq_b", ENC(0, 31), 0, input_port, },
- /* SIC1 */
- { "gptimer@0", ENC(1, 0), 0, input_port, },
- { "gptimer@1", ENC(1, 1), 0, input_port, },
- { "gptimer@2", ENC(1, 2), 0, input_port, },
- { "gptimer@3", ENC(1, 3), 0, input_port, },
- { "gptimer@4", ENC(1, 4), 0, input_port, },
- { "gptimer@5", ENC(1, 5), 0, input_port, },
- { "gptimer@6", ENC(1, 6), 0, input_port, },
- { "gptimer@7", ENC(1, 7), 0, input_port, },
- { "portg_irq_a", ENC(1, 8), 0, input_port, },
- { "portg_irq_b", ENC(1, 9), 0, input_port, },
- { "mdma@0", ENC(1, 10), 0, input_port, },
- { "mdma@1", ENC(1, 11), 0, input_port, },
- { "wdog", ENC(1, 12), 0, input_port, },
- { "portf_irq_a", ENC(1, 13), 0, input_port, },
- { "portf_irq_b", ENC(1, 14), 0, input_port, },
- { "spi@0", ENC(1, 15), 0, input_port, },
- { "spi@1", ENC(1, 16), 0, input_port, },
-/*{ "reserved", ENC(1, 17), 0, input_port, },*/
-/*{ "reserved", ENC(1, 18), 0, input_port, },*/
- { "rsi_int0", ENC(1, 19), 0, input_port, },
- { "rsi_int1", ENC(1, 20), 0, input_port, },
- { "pwm_trip", ENC(1, 21), 0, input_port, },
- { "pwm_sync", ENC(1, 22), 0, input_port, },
- { "ptp_stat", ENC(1, 23), 0, input_port, },
+ SIC_PORTS(0)
+ SIC_PORTS(1)
+ SIC_PORTS(2)
{ NULL, 0, 0, 0, },
};
-static const struct hw_port_descriptor bfin_sic_52x_ports[] =
+static const struct hw_port_descriptor bfin_sic_561_ports[] =
{
+ { "sup_irq@0", 0, 0, output_port, },
+ { "sup_irq@1", 1, 0, output_port, },
BFIN_SIC_TO_CEC_PORTS
- /* SIC0 */
- { "pll", ENC(0, 0), 0, input_port, },
- { "dma_stat", ENC(0, 1), 0, input_port, },
- { "dmar0_block", ENC(0, 2), 0, input_port, },
- { "dmar1_block", ENC(0, 3), 0, input_port, },
- { "dmar0_over", ENC(0, 4), 0, input_port, },
- { "dmar1_over", ENC(0, 5), 0, input_port, },
- { "ppi@0", ENC(0, 6), 0, input_port, },
- { "emac_stat", ENC(0, 7), 0, input_port, },
- { "sport@0_stat", ENC(0, 8), 0, input_port, },
- { "sport@1_stat", ENC(0, 9), 0, input_port, },
-/*{ "reserved", ENC(0, 10), 0, input_port, },*/
-/*{ "reserved", ENC(0, 11), 0, input_port, },*/
- { "uart@0_stat", ENC(0, 12), 0, input_port, },
- { "uart@1_stat", ENC(0, 13), 0, input_port, },
- { "rtc", ENC(0, 14), 0, input_port, },
- { "dma@0", ENC(0, 15), 0, input_port, },
- { "dma@3", ENC(0, 16), 0, input_port, },
- { "dma@4", ENC(0, 17), 0, input_port, },
- { "dma@5", ENC(0, 18), 0, input_port, },
- { "dma@6", ENC(0, 19), 0, input_port, },
- { "twi@0", ENC(0, 20), 0, input_port, },
- { "dma@7", ENC(0, 21), 0, input_port, },
- { "dma@8", ENC(0, 22), 0, input_port, },
- { "dma@9", ENC(0, 23), 0, input_port, },
- { "dma@10", ENC(0, 24), 0, input_port, },
- { "dma@11", ENC(0, 25), 0, input_port, },
- { "otp", ENC(0, 26), 0, input_port, },
- { "counter", ENC(0, 27), 0, input_port, },
- { "dma@1", ENC(0, 28), 0, input_port, },
- { "porth_irq_a", ENC(0, 29), 0, input_port, },
- { "dma@2", ENC(0, 30), 0, input_port, },
- { "porth_irq_b", ENC(0, 31), 0, input_port, },
- /* SIC1 */
- { "gptimer@0", ENC(1, 0), 0, input_port, },
- { "gptimer@1", ENC(1, 1), 0, input_port, },
- { "gptimer@2", ENC(1, 2), 0, input_port, },
- { "gptimer@3", ENC(1, 3), 0, input_port, },
- { "gptimer@4", ENC(1, 4), 0, input_port, },
- { "gptimer@5", ENC(1, 5), 0, input_port, },
- { "gptimer@6", ENC(1, 6), 0, input_port, },
- { "gptimer@7", ENC(1, 7), 0, input_port, },
- { "portg_irq_a", ENC(1, 8), 0, input_port, },
- { "portg_irq_b", ENC(1, 9), 0, input_port, },
- { "mdma@0", ENC(1, 10), 0, input_port, },
- { "mdma@1", ENC(1, 11), 0, input_port, },
- { "wdog", ENC(1, 12), 0, input_port, },
- { "portf_irq_a", ENC(1, 13), 0, input_port, },
- { "portf_irq_b", ENC(1, 14), 0, input_port, },
- { "spi@0", ENC(1, 15), 0, input_port, },
- { "nfc_stat", ENC(1, 16), 0, input_port, },
- { "hostdp_stat", ENC(1, 17), 0, input_port, },
- { "hostdp_done", ENC(1, 18), 0, input_port, },
- { "usb_int0", ENC(1, 20), 0, input_port, },
- { "usb_int1", ENC(1, 21), 0, input_port, },
- { "usb_int2", ENC(1, 22), 0, input_port, },
+ SIC_PORTS(0)
+ SIC_PORTS(1)
{ NULL, 0, 0, 0, },
};
bfin_sic_52x_forward_interrupts (me, sic);
}
-static const struct hw_port_descriptor bfin_sic_533_ports[] =
-{
- BFIN_SIC_TO_CEC_PORTS
- { "pll", ENC(0, 0), 0, input_port, },
- { "dma_stat", ENC(0, 1), 0, input_port, },
- { "ppi@0", ENC(0, 2), 0, input_port, },
- { "sport@0_stat", ENC(0, 3), 0, input_port, },
- { "sport@1_stat", ENC(0, 4), 0, input_port, },
- { "spi@0", ENC(0, 5), 0, input_port, },
- { "uart@0_stat", ENC(0, 6), 0, input_port, },
- { "rtc", ENC(0, 7), 0, input_port, },
- { "dma@0", ENC(0, 8), 0, input_port, },
- { "dma@1", ENC(0, 9), 0, input_port, },
- { "dma@2", ENC(0, 10), 0, input_port, },
- { "dma@3", ENC(0, 11), 0, input_port, },
- { "dma@4", ENC(0, 12), 0, input_port, },
- { "dma@5", ENC(0, 13), 0, input_port, },
- { "dma@6", ENC(0, 14), 0, input_port, },
- { "dma@7", ENC(0, 15), 0, input_port, },
- { "gptimer@0", ENC(0, 16), 0, input_port, },
- { "gptimer@1", ENC(0, 17), 0, input_port, },
- { "gptimer@2", ENC(0, 18), 0, input_port, },
- { "portf_irq_a", ENC(0, 19), 0, input_port, },
- { "portf_irq_b", ENC(0, 20), 0, input_port, },
- { "mdma@0", ENC(0, 21), 0, input_port, },
- { "mdma@1", ENC(0, 22), 0, input_port, },
- { "wdog", ENC(0, 23), 0, input_port, },
- { NULL, 0, 0, 0, },
-};
-
-/* The encoding here is uglier due to multiple sources being muxed into
- the same interrupt line. So give each pin an arbitrary "SIC" so that
- the resulting id is unique across all ports. */
-static const struct hw_port_descriptor bfin_sic_537_ports[] =
-{
- BFIN_SIC_TO_CEC_PORTS
- { "pll", ENC(0, 0), 0, input_port, },
- { "dma_stat", ENC(0, 1), 0, input_port, },
- { "dmar0_block", ENC(1, 1), 0, input_port, },
- { "dmar1_block", ENC(2, 1), 0, input_port, },
- { "dmar0_over", ENC(3, 1), 0, input_port, },
- { "dmar1_over", ENC(4, 1), 0, input_port, },
- { "can_stat", ENC(0, 2), 0, input_port, },
- { "emac_stat", ENC(1, 2), 0, input_port, },
- { "sport@0_stat", ENC(2, 2), 0, input_port, },
- { "sport@1_stat", ENC(3, 2), 0, input_port, },
- { "ppi@0", ENC(4, 2), 0, input_port, },
- { "spi@0", ENC(5, 2), 0, input_port, },
- { "uart@0_stat", ENC(6, 2), 0, input_port, },
- { "uart@1_stat", ENC(7, 2), 0, input_port, },
- { "rtc", ENC(0, 3), 0, input_port, },
- { "dma@0", ENC(0, 4), 0, input_port, },
- { "dma@3", ENC(0, 5), 0, input_port, },
- { "dma@4", ENC(0, 6), 0, input_port, },
- { "dma@5", ENC(0, 7), 0, input_port, },
- { "dma@6", ENC(0, 8), 0, input_port, },
- { "twi@0", ENC(0, 9), 0, input_port, },
- { "dma@7", ENC(0, 10), 0, input_port, },
- { "dma@8", ENC(0, 11), 0, input_port, },
- { "dma@9", ENC(0, 12), 0, input_port, },
- { "dma@10", ENC(0, 13), 0, input_port, },
- { "dma@11", ENC(0, 14), 0, input_port, },
- { "can_rx", ENC(0, 15), 0, input_port, },
- { "can_tx", ENC(0, 16), 0, input_port, },
- { "dma@1", ENC(0, 17), 0, input_port, },
- { "porth_irq_a", ENC(1, 17), 0, input_port, },
- { "dma@2", ENC(0, 18), 0, input_port, },
- { "porth_irq_b", ENC(1, 18), 0, input_port, },
- { "gptimer@0", ENC(0, 19), 0, input_port, },
- { "gptimer@1", ENC(0, 20), 0, input_port, },
- { "gptimer@2", ENC(0, 21), 0, input_port, },
- { "gptimer@3", ENC(0, 22), 0, input_port, },
- { "gptimer@4", ENC(0, 23), 0, input_port, },
- { "gptimer@5", ENC(0, 24), 0, input_port, },
- { "gptimer@6", ENC(0, 25), 0, input_port, },
- { "gptimer@7", ENC(0, 26), 0, input_port, },
- { "portf_irq_a", ENC(0, 27), 0, input_port, },
- { "portg_irq_a", ENC(1, 27), 0, input_port, },
- { "portg_irq_b", ENC(0, 28), 0, input_port, },
- { "mdma@0", ENC(0, 29), 0, input_port, },
- { "mdma@1", ENC(0, 30), 0, input_port, },
- { "wdog", ENC(0, 31), 0, input_port, },
- { "portf_irq_b", ENC(1, 31), 0, input_port, },
- { NULL, 0, 0, 0, },
-};
-
static void
bfin_sic_537_port_event (struct hw *me, int my_port, struct hw *source,
int source_port, int level)
bfin_sic_537_forward_interrupts (me, sic);
}
-static const struct hw_port_descriptor bfin_sic_538_ports[] =
-{
- BFIN_SIC_TO_CEC_PORTS
- /* SIC0 */
- { "pll", ENC(0, 0), 0, input_port, },
- { "dmac@0_stat", ENC(0, 1), 0, input_port, },
- { "ppi@0", ENC(0, 2), 0, input_port, },
- { "sport@0_stat", ENC(0, 3), 0, input_port, },
- { "sport@1_stat", ENC(0, 4), 0, input_port, },
- { "spi@0", ENC(0, 5), 0, input_port, },
- { "uart@0_stat", ENC(0, 6), 0, input_port, },
- { "rtc", ENC(0, 7), 0, input_port, },
- { "dma@0", ENC(0, 8), 0, input_port, },
- { "dma@1", ENC(0, 9), 0, input_port, },
- { "dma@2", ENC(0, 10), 0, input_port, },
- { "dma@3", ENC(0, 11), 0, input_port, },
- { "dma@4", ENC(0, 12), 0, input_port, },
- { "dma@5", ENC(0, 13), 0, input_port, },
- { "dma@6", ENC(0, 14), 0, input_port, },
- { "dma@7", ENC(0, 15), 0, input_port, },
- { "gptimer@0", ENC(0, 16), 0, input_port, },
- { "gptimer@1", ENC(0, 17), 0, input_port, },
- { "gptimer@2", ENC(0, 18), 0, input_port, },
- { "portf_irq_a", ENC(0, 19), 0, input_port, },
- { "portf_irq_b", ENC(0, 20), 0, input_port, },
- { "mdma@0", ENC(0, 21), 0, input_port, },
- { "mdma@1", ENC(0, 22), 0, input_port, },
- { "wdog", ENC(0, 23), 0, input_port, },
- { "dmac@1_stat", ENC(0, 24), 0, input_port, },
- { "sport@2_stat", ENC(0, 25), 0, input_port, },
- { "sport@3_stat", ENC(0, 26), 0, input_port, },
-/*{ "reserved", ENC(0, 27), 0, input_port, },*/
- { "spi@1", ENC(0, 28), 0, input_port, },
- { "spi@2", ENC(0, 29), 0, input_port, },
- { "uart@1_stat", ENC(0, 30), 0, input_port, },
- { "uart@2_stat", ENC(0, 31), 0, input_port, },
- /* SIC1 */
- { "can_stat", ENC(1, 0), 0, input_port, },
- { "dma@8", ENC(1, 1), 0, input_port, },
- { "dma@9", ENC(1, 2), 0, input_port, },
- { "dma@10", ENC(1, 3), 0, input_port, },
- { "dma@11", ENC(1, 4), 0, input_port, },
- { "dma@12", ENC(1, 5), 0, input_port, },
- { "dma@13", ENC(1, 6), 0, input_port, },
- { "dma@14", ENC(1, 7), 0, input_port, },
- { "dma@15", ENC(1, 8), 0, input_port, },
- { "dma@16", ENC(1, 9), 0, input_port, },
- { "dma@17", ENC(1, 10), 0, input_port, },
- { "dma@18", ENC(1, 11), 0, input_port, },
- { "dma@19", ENC(1, 12), 0, input_port, },
- { "twi@0", ENC(1, 13), 0, input_port, },
- { "twi@1", ENC(1, 14), 0, input_port, },
- { "can_rx", ENC(1, 15), 0, input_port, },
- { "can_tx", ENC(1, 16), 0, input_port, },
- { "mdma@2", ENC(1, 17), 0, input_port, },
- { "mdma@3", ENC(1, 18), 0, input_port, },
- { NULL, 0, 0, 0, },
-};
-
-static const struct hw_port_descriptor bfin_sic_54x_ports[] =
-{
- BFIN_SIC_TO_CEC_PORTS
- /* SIC0 */
- { "pll", ENC(0, 0), 0, input_port, },
- { "dmac@0_stat", ENC(0, 1), 0, input_port, },
- { "eppi@0", ENC(0, 2), 0, input_port, },
- { "sport@0_stat", ENC(0, 3), 0, input_port, },
- { "sport@1_stat", ENC(0, 4), 0, input_port, },
- { "spi@0", ENC(0, 5), 0, input_port, },
- { "uart2@0_stat", ENC(0, 6), 0, input_port, },
- { "rtc", ENC(0, 7), 0, input_port, },
- { "dma@12", ENC(0, 8), 0, input_port, },
- { "dma@0", ENC(0, 9), 0, input_port, },
- { "dma@1", ENC(0, 10), 0, input_port, },
- { "dma@2", ENC(0, 11), 0, input_port, },
- { "dma@3", ENC(0, 12), 0, input_port, },
- { "dma@4", ENC(0, 13), 0, input_port, },
- { "dma@6", ENC(0, 14), 0, input_port, },
- { "dma@7", ENC(0, 15), 0, input_port, },
- { "gptimer@8", ENC(0, 16), 0, input_port, },
- { "gptimer@9", ENC(0, 17), 0, input_port, },
- { "gptimer@10", ENC(0, 18), 0, input_port, },
- { "pint@0", ENC(0, 19), 0, input_port, },
- { "pint@1", ENC(0, 20), 0, input_port, },
- { "mdma@0", ENC(0, 21), 0, input_port, },
- { "mdma@1", ENC(0, 22), 0, input_port, },
- { "wdog", ENC(0, 23), 0, input_port, },
- { "dmac@1_stat", ENC(0, 24), 0, input_port, },
- { "sport@2_stat", ENC(0, 25), 0, input_port, },
- { "sport@3_stat", ENC(0, 26), 0, input_port, },
- { "mxvr", ENC(0, 27), 0, input_port, },
- { "spi@1", ENC(0, 28), 0, input_port, },
- { "spi@2", ENC(0, 29), 0, input_port, },
- { "uart2@1_stat", ENC(0, 30), 0, input_port, },
- { "uart2@2_stat", ENC(0, 31), 0, input_port, },
- /* SIC1 */
- { "can@0_stat", ENC(1, 0), 0, input_port, },
- { "dma@18", ENC(1, 1), 0, input_port, },
- { "dma@19", ENC(1, 2), 0, input_port, },
- { "dma@20", ENC(1, 3), 0, input_port, },
- { "dma@21", ENC(1, 4), 0, input_port, },
- { "dma@13", ENC(1, 5), 0, input_port, },
- { "dma@14", ENC(1, 6), 0, input_port, },
- { "dma@5", ENC(1, 7), 0, input_port, },
- { "dma@23", ENC(1, 8), 0, input_port, },
- { "dma@8", ENC(1, 9), 0, input_port, },
- { "dma@9", ENC(1, 10), 0, input_port, },
- { "dma@10", ENC(1, 11), 0, input_port, },
- { "dma@11", ENC(1, 12), 0, input_port, },
- { "twi@0", ENC(1, 13), 0, input_port, },
- { "twi@1", ENC(1, 14), 0, input_port, },
- { "can@0_rx", ENC(1, 15), 0, input_port, },
- { "can@0_tx", ENC(1, 16), 0, input_port, },
- { "mdma@2", ENC(1, 17), 0, input_port, },
- { "mdma@3", ENC(1, 18), 0, input_port, },
- { "mxvr_stat", ENC(1, 19), 0, input_port, },
- { "mxvr_message", ENC(1, 20), 0, input_port, },
- { "mxvr_packet", ENC(1, 21), 0, input_port, },
- { "eppi@1", ENC(1, 22), 0, input_port, },
- { "eppi@2", ENC(1, 23), 0, input_port, },
- { "uart2@3_stat", ENC(1, 24), 0, input_port, },
- { "hostdp", ENC(1, 25), 0, input_port, },
-/*{ "reserved", ENC(1, 26), 0, input_port, },*/
- { "pixc_stat", ENC(1, 27), 0, input_port, },
- { "nfc", ENC(1, 28), 0, input_port, },
- { "atapi", ENC(1, 29), 0, input_port, },
- { "can@1_stat", ENC(1, 30), 0, input_port, },
- { "dmar", ENC(1, 31), 0, input_port, },
- /* SIC2 */
- { "dma@15", ENC(2, 0), 0, input_port, },
- { "dma@16", ENC(2, 1), 0, input_port, },
- { "dma@17", ENC(2, 2), 0, input_port, },
- { "dma@22", ENC(2, 3), 0, input_port, },
- { "counter", ENC(2, 4), 0, input_port, },
- { "key", ENC(2, 5), 0, input_port, },
- { "can@1_rx", ENC(2, 6), 0, input_port, },
- { "can@1_tx", ENC(2, 7), 0, input_port, },
- { "sdh_mask0", ENC(2, 8), 0, input_port, },
- { "sdh_mask1", ENC(2, 9), 0, input_port, },
-/*{ "reserved", ENC(2, 10), 0, input_port, },*/
- { "usb_int0", ENC(2, 11), 0, input_port, },
- { "usb_int1", ENC(2, 12), 0, input_port, },
- { "usb_int2", ENC(2, 13), 0, input_port, },
- { "usb_dma", ENC(2, 14), 0, input_port, },
- { "otpsec", ENC(2, 15), 0, input_port, },
-/*{ "reserved", ENC(2, 16), 0, input_port, },*/
-/*{ "reserved", ENC(2, 17), 0, input_port, },*/
-/*{ "reserved", ENC(2, 18), 0, input_port, },*/
-/*{ "reserved", ENC(2, 19), 0, input_port, },*/
-/*{ "reserved", ENC(2, 20), 0, input_port, },*/
-/*{ "reserved", ENC(2, 21), 0, input_port, },*/
- { "gptimer@0", ENC(2, 22), 0, input_port, },
- { "gptimer@1", ENC(2, 23), 0, input_port, },
- { "gptimer@2", ENC(2, 24), 0, input_port, },
- { "gptimer@3", ENC(2, 25), 0, input_port, },
- { "gptimer@4", ENC(2, 26), 0, input_port, },
- { "gptimer@5", ENC(2, 27), 0, input_port, },
- { "gptimer@6", ENC(2, 28), 0, input_port, },
- { "gptimer@7", ENC(2, 29), 0, input_port, },
- { "pint2", ENC(2, 30), 0, input_port, },
- { "pint3", ENC(2, 31), 0, input_port, },
- { NULL, 0, 0, 0, },
-};
-
static void
bfin_sic_54x_port_event (struct hw *me, int my_port, struct hw *source,
int source_port, int level)
bfin_sic_54x_forward_interrupts (me, sic);
}
-static const struct hw_port_descriptor bfin_sic_561_ports[] =
-{
- BFIN_SIC_TO_CEC_PORTS
- /* SIC0 */
- { "pll", ENC(0, 0), 0, input_port, },
- { "dmac@0_stat", ENC(0, 1), 0, input_port, },
- { "dmac@1_stat", ENC(0, 2), 0, input_port, },
- { "imdma_stat", ENC(0, 3), 0, input_port, },
- { "ppi@0", ENC(0, 4), 0, input_port, },
- { "ppi@1", ENC(0, 5), 0, input_port, },
- { "sport@0_stat", ENC(0, 6), 0, input_port, },
- { "sport@1_stat", ENC(0, 7), 0, input_port, },
- { "spi@0", ENC(0, 8), 0, input_port, },
- { "uart@0_stat", ENC(0, 9), 0, input_port, },
-/*{ "reserved", ENC(0, 10), 0, input_port, },*/
- { "dma@12", ENC(0, 11), 0, input_port, },
- { "dma@13", ENC(0, 12), 0, input_port, },
- { "dma@14", ENC(0, 13), 0, input_port, },
- { "dma@15", ENC(0, 14), 0, input_port, },
- { "dma@16", ENC(0, 15), 0, input_port, },
- { "dma@17", ENC(0, 16), 0, input_port, },
- { "dma@18", ENC(0, 17), 0, input_port, },
- { "dma@19", ENC(0, 18), 0, input_port, },
- { "dma@20", ENC(0, 19), 0, input_port, },
- { "dma@21", ENC(0, 20), 0, input_port, },
- { "dma@22", ENC(0, 21), 0, input_port, },
- { "dma@23", ENC(0, 22), 0, input_port, },
- { "dma@0", ENC(0, 23), 0, input_port, },
- { "dma@1", ENC(0, 24), 0, input_port, },
- { "dma@2", ENC(0, 25), 0, input_port, },
- { "dma@3", ENC(0, 26), 0, input_port, },
- { "dma@4", ENC(0, 27), 0, input_port, },
- { "dma@5", ENC(0, 28), 0, input_port, },
- { "dma@6", ENC(0, 29), 0, input_port, },
- { "dma@7", ENC(0, 30), 0, input_port, },
- { "dma@8", ENC(0, 31), 0, input_port, },
- /* SIC1 */
- { "dma@9", ENC(1, 0), 0, input_port, },
- { "dma@10", ENC(1, 1), 0, input_port, },
- { "dma@11", ENC(1, 2), 0, input_port, },
- { "gptimer@0", ENC(1, 3), 0, input_port, },
- { "gptimer@1", ENC(1, 4), 0, input_port, },
- { "gptimer@2", ENC(1, 5), 0, input_port, },
- { "gptimer@3", ENC(1, 6), 0, input_port, },
- { "gptimer@4", ENC(1, 7), 0, input_port, },
- { "gptimer@5", ENC(1, 8), 0, input_port, },
- { "gptimer@6", ENC(1, 9), 0, input_port, },
- { "gptimer@7", ENC(1, 10), 0, input_port, },
- { "gptimer@8", ENC(1, 11), 0, input_port, },
- { "gptimer@9", ENC(1, 12), 0, input_port, },
- { "gptimer@10", ENC(1, 13), 0, input_port, },
- { "gptimer@11", ENC(1, 14), 0, input_port, },
- { "portf_irq_a", ENC(1, 15), 0, input_port, },
- { "portf_irq_b", ENC(1, 16), 0, input_port, },
- { "portg_irq_a", ENC(1, 17), 0, input_port, },
- { "portg_irq_b", ENC(1, 18), 0, input_port, },
- { "porth_irq_a", ENC(1, 19), 0, input_port, },
- { "porth_irq_b", ENC(1, 20), 0, input_port, },
- { "mdma@0", ENC(1, 21), 0, input_port, },
- { "mdma@1", ENC(1, 22), 0, input_port, },
- { "mdma@2", ENC(1, 23), 0, input_port, },
- { "mdma@3", ENC(1, 24), 0, input_port, },
- { "imdma@0", ENC(1, 25), 0, input_port, },
- { "imdma@1", ENC(1, 26), 0, input_port, },
- { "wdog", ENC(1, 27), 0, input_port, },
-/*{ "reserved", ENC(1, 28), 0, input_port, },*/
-/*{ "reserved", ENC(1, 29), 0, input_port, },*/
- { "sup_irq_0", ENC(1, 30), 0, input_port, },
- { "sup_irq_1", ENC(1, 31), 0, input_port, },
- { NULL, 0, 0, 0, },
-};
-
static void
bfin_sic_561_port_event (struct hw *me, int my_port, struct hw *source,
int source_port, int level)
bfin_sic_561_forward_interrupts (me, sic);
}
-static const struct hw_port_descriptor bfin_sic_59x_ports[] =
-{
- BFIN_SIC_TO_CEC_PORTS
- { "pll", ENC(0, 0), 0, input_port, },
- { "dma_stat", ENC(0, 1), 0, input_port, },
- { "ppi@0", ENC(0, 2), 0, input_port, },
- { "sport@0_stat", ENC(0, 3), 0, input_port, },
- { "sport@1_stat", ENC(0, 4), 0, input_port, },
- { "spi@0", ENC(0, 5), 0, input_port, },
- { "spi@1", ENC(0, 6), 0, input_port, },
- { "uart@0_stat", ENC(0, 7), 0, input_port, },
- { "dma@0", ENC(0, 8), 0, input_port, },
- { "dma@1", ENC(0, 9), 0, input_port, },
- { "dma@2", ENC(0, 10), 0, input_port, },
- { "dma@3", ENC(0, 11), 0, input_port, },
- { "dma@4", ENC(0, 12), 0, input_port, },
- { "dma@5", ENC(0, 13), 0, input_port, },
- { "dma@6", ENC(0, 14), 0, input_port, },
- { "dma@7", ENC(0, 15), 0, input_port, },
- { "dma@8", ENC(0, 16), 0, input_port, },
- { "portf_irq_a", ENC(0, 17), 0, input_port, },
- { "portf_irq_b", ENC(0, 18), 0, input_port, },
- { "gptimer@0", ENC(0, 19), 0, input_port, },
- { "gptimer@1", ENC(0, 20), 0, input_port, },
- { "gptimer@2", ENC(0, 21), 0, input_port, },
- { "portg_irq_a", ENC(0, 22), 0, input_port, },
- { "portg_irq_b", ENC(0, 23), 0, input_port, },
- { "twi@0", ENC(0, 24), 0, input_port, },
-/* XXX: 25 - 28 are supposed to be reserved; see comment in machs.c:bf592_dmac[] */
- { "dma@9", ENC(0, 25), 0, input_port, },
- { "dma@10", ENC(0, 26), 0, input_port, },
- { "dma@11", ENC(0, 27), 0, input_port, },
- { "dma@12", ENC(0, 28), 0, input_port, },
-/*{ "reserved", ENC(0, 25), 0, input_port, },*/
-/*{ "reserved", ENC(0, 26), 0, input_port, },*/
-/*{ "reserved", ENC(0, 27), 0, input_port, },*/
-/*{ "reserved", ENC(0, 28), 0, input_port, },*/
- { "mdma@0", ENC(0, 29), 0, input_port, },
- { "mdma@1", ENC(0, 30), 0, input_port, },
- { "wdog", ENC(0, 31), 0, input_port, },
- { NULL, 0, 0, 0, },
-};
-
static void
attach_bfin_sic_regs (struct hw *me, struct bfin_sic *sic)
{
case 500 ... 509:
set_hw_io_read_buffer (me, bfin_sic_52x_io_read_buffer);
set_hw_io_write_buffer (me, bfin_sic_52x_io_write_buffer);
- set_hw_ports (me, bfin_sic_50x_ports);
+ set_hw_ports (me, bfin_sic2_ports);
set_hw_port_event (me, bfin_sic_52x_port_event);
mmr_names = bf52x_mmr_names;
case 510 ... 519:
set_hw_io_read_buffer (me, bfin_sic_52x_io_read_buffer);
set_hw_io_write_buffer (me, bfin_sic_52x_io_write_buffer);
- set_hw_ports (me, bfin_sic_51x_ports);
+ set_hw_ports (me, bfin_sic2_ports);
set_hw_port_event (me, bfin_sic_52x_port_event);
mmr_names = bf52x_mmr_names;
case 522 ... 527:
set_hw_io_read_buffer (me, bfin_sic_52x_io_read_buffer);
set_hw_io_write_buffer (me, bfin_sic_52x_io_write_buffer);
- set_hw_ports (me, bfin_sic_52x_ports);
+ set_hw_ports (me, bfin_sic2_ports);
set_hw_port_event (me, bfin_sic_52x_port_event);
mmr_names = bf52x_mmr_names;
case 531 ... 533:
set_hw_io_read_buffer (me, bfin_sic_537_io_read_buffer);
set_hw_io_write_buffer (me, bfin_sic_537_io_write_buffer);
- set_hw_ports (me, bfin_sic_533_ports);
+ set_hw_ports (me, bfin_sic1_ports);
set_hw_port_event (me, bfin_sic_537_port_event);
mmr_names = bf537_mmr_names;
case 537:
set_hw_io_read_buffer (me, bfin_sic_537_io_read_buffer);
set_hw_io_write_buffer (me, bfin_sic_537_io_write_buffer);
- set_hw_ports (me, bfin_sic_537_ports);
+ set_hw_ports (me, bfin_sic1_ports);
set_hw_port_event (me, bfin_sic_537_port_event);
mmr_names = bf537_mmr_names;
case 538 ... 539:
set_hw_io_read_buffer (me, bfin_sic_52x_io_read_buffer);
set_hw_io_write_buffer (me, bfin_sic_52x_io_write_buffer);
- set_hw_ports (me, bfin_sic_538_ports);
+ set_hw_ports (me, bfin_sic2_ports);
set_hw_port_event (me, bfin_sic_52x_port_event);
mmr_names = bf52x_mmr_names;
case 540 ... 549:
set_hw_io_read_buffer (me, bfin_sic_54x_io_read_buffer);
set_hw_io_write_buffer (me, bfin_sic_54x_io_write_buffer);
- set_hw_ports (me, bfin_sic_54x_ports);
+ set_hw_ports (me, bfin_sic3_ports);
set_hw_port_event (me, bfin_sic_54x_port_event);
mmr_names = bf54x_mmr_names;
case 590 ... 599:
set_hw_io_read_buffer (me, bfin_sic_537_io_read_buffer);
set_hw_io_write_buffer (me, bfin_sic_537_io_write_buffer);
- set_hw_ports (me, bfin_sic_59x_ports);
+ set_hw_ports (me, bfin_sic1_ports);
set_hw_port_event (me, bfin_sic_537_port_event);
mmr_names = bf537_mmr_names;
address_word base;
unsigned int dma_count;
};
+struct bfin_port_layout {
+ /* Which device this routes to (name/port). */
+ const char *dst, *dst_port;
+ /* Which device this routes from (name/port). */
+ const char *src, *src_port;
+};
struct bfin_model_data {
bu32 chipid;
int model_num;
size_t dev_count;
const struct bfin_dmac_layout *dmac;
size_t dmac_count;
+ const struct bfin_port_layout *port;
+ size_t port_count;
};
#define LAYOUT(_addr, _len, _mask) { .addr = _addr, .len = _len, .mask = access_##_mask, }
#define _DEVICE(_base, _len, _dev, _dmac) { .base = _base, .len = _len, .dev = _dev, .dmac = _dmac, }
#define DEVICE(_base, _len, _dev) _DEVICE(_base, _len, _dev, 0)
+#define PORT(_dst, _dst_port, _src, _src_port) \
+ { \
+ .dst = _dst, \
+ .dst_port = _dst_port, \
+ .src = _src, \
+ .src_port = _src_port, \
+ }
+#define SIC(_s, _ip, _d, _op) PORT("bfin_sic", "int"#_ip"@"#_s, _d, _op)
/* [1] Common sim code can't model exec-only memory.
http://sourceware.org/ml/gdb/2010-02/msg00047.html */
static const struct bfin_memory_layout bf000_mem[] = {};
static const struct bfin_dev_layout bf000_dev[] = {};
static const struct bfin_dmac_layout bf000_dmac[] = {};
+static const struct bfin_port_layout bf000_port[] = {};
#define bf50x_chipid 0x2800
#define bf504_chipid bf50x_chipid
};
#define bf504_dmac bf50x_dmac
#define bf506_dmac bf50x_dmac
+static const struct bfin_port_layout bf50x_port[] =
+{
+ SIC (0, 0, "bfin_pll", "pll"),
+/*SIC (0, 1, "bfin_dmac@0", "stat"),*/
+ SIC (0, 2, "bfin_ppi@0", "stat"),
+ SIC (0, 3, "bfin_sport@0", "stat"),
+ SIC (0, 4, "bfin_sport@1", "stat"),
+ SIC (0, 5, "bfin_uart2@0", "stat"),
+ SIC (0, 6, "bfin_uart2@1", "stat"),
+ SIC (0, 7, "bfin_spi@0", "stat"),
+ SIC (0, 8, "bfin_spi@1", "stat"),
+ SIC (0, 9, "bfin_can@0", "stat"),
+ SIC (0, 10, "bfin_rsi@0", "int0"),
+/*SIC (0, 11, reserved),*/
+ SIC (0, 12, "bfin_counter@0", "stat"),
+ SIC (0, 13, "bfin_counter@1", "stat"),
+ SIC (0, 14, "bfin_dma@0", "di"),
+ SIC (0, 15, "bfin_dma@1", "di"),
+ SIC (0, 16, "bfin_dma@2", "di"),
+ SIC (0, 17, "bfin_dma@3", "di"),
+ SIC (0, 18, "bfin_dma@4", "di"),
+ SIC (0, 19, "bfin_dma@5", "di"),
+ SIC (0, 20, "bfin_dma@6", "di"),
+ SIC (0, 21, "bfin_dma@7", "di"),
+ SIC (0, 22, "bfin_dma@8", "di"),
+ SIC (0, 23, "bfin_dma@9", "di"),
+ SIC (0, 24, "bfin_dma@10", "di"),
+ SIC (0, 25, "bfin_dma@11", "di"),
+ SIC (0, 26, "bfin_can@0", "rx"),
+ SIC (0, 27, "bfin_can@0", "tx"),
+ SIC (0, 28, "bfin_twi@0", "stat"),
+ SIC (0, 29, "bfin_gpio@5", "mask_a"),
+ SIC (0, 30, "bfin_gpio@5", "mask_b"),
+/*SIC (0, 31, reserved),*/
+ SIC (1, 0, "bfin_gptimer@0", "stat"),
+ SIC (1, 1, "bfin_gptimer@1", "stat"),
+ SIC (1, 2, "bfin_gptimer@2", "stat"),
+ SIC (1, 3, "bfin_gptimer@3", "stat"),
+ SIC (1, 4, "bfin_gptimer@4", "stat"),
+ SIC (1, 5, "bfin_gptimer@5", "stat"),
+ SIC (1, 6, "bfin_gptimer@6", "stat"),
+ SIC (1, 7, "bfin_gptimer@7", "stat"),
+ SIC (1, 8, "bfin_gpio@6", "mask_a"),
+ SIC (1, 9, "bfin_gpio@6", "mask_b"),
+ SIC (1, 10, "bfin_dma@256", "di"), /* mdma0 */
+ SIC (1, 10, "bfin_dma@257", "di"), /* mdma0 */
+ SIC (1, 11, "bfin_dma@258", "di"), /* mdma1 */
+ SIC (1, 11, "bfin_dma@259", "di"), /* mdma1 */
+ SIC (1, 12, "bfin_wdog@0", "gpi"),
+ SIC (1, 13, "bfin_gpio@7", "mask_a"),
+ SIC (1, 14, "bfin_gpio@7", "mask_b"),
+ SIC (1, 15, "bfin_acm@0", "stat"),
+ SIC (1, 16, "bfin_acm@1", "int"),
+/*SIC (1, 17, reserved),*/
+/*SIC (1, 18, reserved),*/
+ SIC (1, 19, "bfin_pwm@0", "trip"),
+ SIC (1, 20, "bfin_pwm@0", "sync"),
+ SIC (1, 21, "bfin_pwm@1", "trip"),
+ SIC (1, 22, "bfin_pwm@1", "sync"),
+ SIC (1, 23, "bfin_rsi@0", "int1"),
+};
+#define bf504_port bf50x_port
+#define bf506_port bf50x_port
#define bf51x_chipid 0x27e8
#define bf512_chipid bf51x_chipid
#define bf514_dmac bf50x_dmac
#define bf516_dmac bf50x_dmac
#define bf518_dmac bf50x_dmac
+static const struct bfin_port_layout bf51x_port[] =
+{
+ SIC (0, 0, "bfin_pll", "pll"),
+/*SIC (0, 1, "bfin_dmac@0", "stat"),*/
+ SIC (0, 2, "bfin_dmar@0", "block"),
+ SIC (0, 3, "bfin_dmar@1", "block"),
+ SIC (0, 4, "bfin_dmar@0", "overflow"),
+ SIC (0, 5, "bfin_dmar@1", "overflow"),
+ SIC (0, 6, "bfin_ppi@0", "stat"),
+ SIC (0, 7, "bfin_emac", "stat"),
+ SIC (0, 8, "bfin_sport@0", "stat"),
+ SIC (0, 9, "bfin_sport@1", "stat"),
+ SIC (0, 10, "bfin_ptp", "stat"),
+/*SIC (0, 11, reserved),*/
+ SIC (0, 12, "bfin_uart@0", "stat"),
+ SIC (0, 13, "bfin_uart@1", "stat"),
+ SIC (0, 14, "bfin_rtc", "rtc"),
+ SIC (0, 15, "bfin_dma@0", "di"),
+ SIC (0, 16, "bfin_dma@3", "di"),
+ SIC (0, 17, "bfin_dma@4", "di"),
+ SIC (0, 18, "bfin_dma@5", "di"),
+ SIC (0, 19, "bfin_dma@6", "di"),
+ SIC (0, 20, "bfin_twi@0", "stat"),
+ SIC (0, 21, "bfin_dma@7", "di"),
+ SIC (0, 22, "bfin_dma@8", "di"),
+ SIC (0, 23, "bfin_dma@9", "di"),
+ SIC (0, 24, "bfin_dma@10", "di"),
+ SIC (0, 25, "bfin_dma@11", "di"),
+ SIC (0, 26, "bfin_otp", "stat"),
+ SIC (0, 27, "bfin_counter@0", "stat"),
+ SIC (0, 28, "bfin_dma@1", "di"),
+ SIC (0, 29, "bfin_gpio@7", "mask_a"),
+ SIC (0, 30, "bfin_dma@2", "di"),
+ SIC (0, 31, "bfin_gpio@7", "mask_b"),
+ SIC (1, 0, "bfin_gptimer@0", "stat"),
+ SIC (1, 1, "bfin_gptimer@1", "stat"),
+ SIC (1, 2, "bfin_gptimer@2", "stat"),
+ SIC (1, 3, "bfin_gptimer@3", "stat"),
+ SIC (1, 4, "bfin_gptimer@4", "stat"),
+ SIC (1, 5, "bfin_gptimer@5", "stat"),
+ SIC (1, 6, "bfin_gptimer@6", "stat"),
+ SIC (1, 7, "bfin_gptimer@7", "stat"),
+ SIC (1, 8, "bfin_gpio@6", "mask_a"),
+ SIC (1, 9, "bfin_gpio@6", "mask_b"),
+ SIC (1, 10, "bfin_dma@256", "di"), /* mdma0 */
+ SIC (1, 10, "bfin_dma@257", "di"), /* mdma0 */
+ SIC (1, 11, "bfin_dma@258", "di"), /* mdma1 */
+ SIC (1, 11, "bfin_dma@259", "di"), /* mdma1 */
+ SIC (1, 12, "bfin_wdog@0", "gpi"),
+ SIC (1, 13, "bfin_gpio@5", "mask_a"),
+ SIC (1, 14, "bfin_gpio@5", "mask_b"),
+ SIC (1, 15, "bfin_spi@0", "stat"),
+ SIC (1, 16, "bfin_spi@1", "stat"),
+/*SIC (1, 17, reserved),*/
+/*SIC (1, 18, reserved),*/
+ SIC (1, 19, "bfin_rsi@0", "int0"),
+ SIC (1, 20, "bfin_rsi@0", "int1"),
+ SIC (1, 21, "bfin_pwm@0", "trip"),
+ SIC (1, 22, "bfin_pwm@0", "sync"),
+ SIC (1, 23, "bfin_ptp", "stat"),
+};
+#define bf512_port bf51x_port
+#define bf514_port bf51x_port
+#define bf516_port bf51x_port
+#define bf518_port bf51x_port
#define bf522_chipid 0x27e4
#define bf523_chipid 0x27e0
#define bf525_dmac bf50x_dmac
#define bf526_dmac bf50x_dmac
#define bf527_dmac bf50x_dmac
+static const struct bfin_port_layout bf52x_port[] =
+{
+ SIC (0, 0, "bfin_pll", "pll"),
+/*SIC (0, 1, "bfin_dmac@0", "stat"),*/
+ SIC (0, 2, "bfin_dmar@0", "block"),
+ SIC (0, 3, "bfin_dmar@1", "block"),
+ SIC (0, 4, "bfin_dmar@0", "overflow"),
+ SIC (0, 5, "bfin_dmar@1", "overflow"),
+ SIC (0, 6, "bfin_ppi@0", "stat"),
+ SIC (0, 7, "bfin_emac", "stat"),
+ SIC (0, 8, "bfin_sport@0", "stat"),
+ SIC (0, 9, "bfin_sport@1", "stat"),
+/*SIC (0, 10, reserved),*/
+/*SIC (0, 11, reserved),*/
+ SIC (0, 12, "bfin_uart@0", "stat"),
+ SIC (0, 13, "bfin_uart@1", "stat"),
+ SIC (0, 14, "bfin_rtc", "rtc"),
+ SIC (0, 15, "bfin_dma@0", "di"),
+ SIC (0, 16, "bfin_dma@3", "di"),
+ SIC (0, 17, "bfin_dma@4", "di"),
+ SIC (0, 18, "bfin_dma@5", "di"),
+ SIC (0, 19, "bfin_dma@6", "di"),
+ SIC (0, 20, "bfin_twi@0", "stat"),
+ SIC (0, 21, "bfin_dma@7", "di"),
+ SIC (0, 22, "bfin_dma@8", "di"),
+ SIC (0, 23, "bfin_dma@9", "di"),
+ SIC (0, 24, "bfin_dma@10", "di"),
+ SIC (0, 25, "bfin_dma@11", "di"),
+ SIC (0, 26, "bfin_otp", "stat"),
+ SIC (0, 27, "bfin_counter@0", "stat"),
+ SIC (0, 28, "bfin_dma@1", "di"),
+ SIC (0, 29, "bfin_gpio@7", "mask_a"),
+ SIC (0, 30, "bfin_dma@2", "di"),
+ SIC (0, 31, "bfin_gpio@7", "mask_b"),
+ SIC (1, 0, "bfin_gptimer@0", "stat"),
+ SIC (1, 1, "bfin_gptimer@1", "stat"),
+ SIC (1, 2, "bfin_gptimer@2", "stat"),
+ SIC (1, 3, "bfin_gptimer@3", "stat"),
+ SIC (1, 4, "bfin_gptimer@4", "stat"),
+ SIC (1, 5, "bfin_gptimer@5", "stat"),
+ SIC (1, 6, "bfin_gptimer@6", "stat"),
+ SIC (1, 7, "bfin_gptimer@7", "stat"),
+ SIC (1, 8, "bfin_gpio@6", "mask_a"),
+ SIC (1, 9, "bfin_gpio@6", "mask_b"),
+ SIC (1, 10, "bfin_dma@256", "di"), /* mdma0 */
+ SIC (1, 10, "bfin_dma@257", "di"), /* mdma0 */
+ SIC (1, 11, "bfin_dma@258", "di"), /* mdma1 */
+ SIC (1, 11, "bfin_dma@259", "di"), /* mdma1 */
+ SIC (1, 12, "bfin_wdog@0", "gpi"),
+ SIC (1, 13, "bfin_gpio@5", "mask_a"),
+ SIC (1, 14, "bfin_gpio@5", "mask_b"),
+ SIC (1, 15, "bfin_spi@0", "stat"),
+ SIC (1, 16, "bfin_nfc", "stat"),
+ SIC (1, 17, "bfin_hostdp", "stat"),
+ SIC (1, 18, "bfin_hostdp", "done"),
+ SIC (1, 20, "bfin_usb", "int0"),
+ SIC (1, 21, "bfin_usb", "int1"),
+ SIC (1, 22, "bfin_usb", "int2"),
+};
+#define bf522_port bf51x_port
+#define bf523_port bf51x_port
+#define bf524_port bf51x_port
+#define bf525_port bf51x_port
+#define bf526_port bf51x_port
+#define bf527_port bf51x_port
#define bf531_chipid 0x27a5
#define bf532_chipid bf531_chipid
};
#define bf531_dmac bf533_dmac
#define bf532_dmac bf533_dmac
+static const struct bfin_port_layout bf533_port[] =
+{
+ SIC (0, 0, "bfin_pll", "pll"),
+/*SIC (0, 1, "bfin_dmac@0", "stat"),*/
+ SIC (0, 2, "bfin_ppi@0", "stat"),
+ SIC (0, 3, "bfin_sport@0", "stat"),
+ SIC (0, 4, "bfin_sport@1", "stat"),
+ SIC (0, 5, "bfin_spi@0", "stat"),
+ SIC (0, 6, "bfin_uart@0", "stat"),
+ SIC (0, 7, "bfin_rtc", "rtc"),
+ SIC (0, 8, "bfin_dma@0", "di"),
+ SIC (0, 9, "bfin_dma@1", "di"),
+ SIC (0, 10, "bfin_dma@2", "di"),
+ SIC (0, 11, "bfin_dma@3", "di"),
+ SIC (0, 12, "bfin_dma@4", "di"),
+ SIC (0, 13, "bfin_dma@5", "di"),
+ SIC (0, 14, "bfin_dma@6", "di"),
+ SIC (0, 15, "bfin_dma@7", "di"),
+ SIC (0, 16, "bfin_gptimer@0", "stat"),
+ SIC (0, 17, "bfin_gptimer@1", "stat"),
+ SIC (0, 18, "bfin_gptimer@2", "stat"),
+ SIC (0, 19, "bfin_gpio@5", "mask_a"),
+ SIC (0, 20, "bfin_gpio@5", "mask_b"),
+ SIC (0, 21, "bfin_dma@256", "di"), /* mdma0 */
+ SIC (0, 21, "bfin_dma@257", "di"), /* mdma0 */
+ SIC (0, 22, "bfin_dma@258", "di"), /* mdma */
+ SIC (0, 22, "bfin_dma@259", "di"), /* mdma1 */
+ SIC (0, 23, "bfin_wdog@0", "gpi"),
+};
+#define bf531_port bf533_port
+#define bf532_port bf533_port
#define bf534_chipid 0x27c6
#define bf536_chipid 0x27c8
#define bf534_dmac bf50x_dmac
#define bf536_dmac bf50x_dmac
#define bf537_dmac bf50x_dmac
+static const struct bfin_port_layout bf537_port[] =
+{
+ SIC (0, 0, "bfin_pll", "pll"),
+/*SIC (0, 1, "bfin_dmac@0", "stat"),*/
+ SIC (0, 1, "bfin_dmar@0", "block"),
+ SIC (0, 1, "bfin_dmar@1", "block"),
+ SIC (0, 1, "bfin_dmar@0", "overflow"),
+ SIC (0, 1, "bfin_dmar@1", "overflow"),
+ SIC (0, 2, "bfin_can@0", "stat"),
+ SIC (0, 2, "bfin_emac", "stat"),
+ SIC (0, 2, "bfin_sport@0", "stat"),
+ SIC (0, 2, "bfin_sport@1", "stat"),
+ SIC (0, 2, "bfin_ppi@0", "stat"),
+ SIC (0, 2, "bfin_spi@0", "stat"),
+ SIC (0, 2, "bfin_uart@0", "stat"),
+ SIC (0, 2, "bfin_uart@1", "stat"),
+ SIC (0, 3, "bfin_rtc", "rtc"),
+ SIC (0, 4, "bfin_dma@0", "di"),
+ SIC (0, 5, "bfin_dma@3", "di"),
+ SIC (0, 6, "bfin_dma@4", "di"),
+ SIC (0, 7, "bfin_dma@5", "di"),
+ SIC (0, 8, "bfin_dma@6", "di"),
+ SIC (0, 9, "bfin_twi@0", "stat"),
+ SIC (0, 10, "bfin_dma@7", "di"),
+ SIC (0, 11, "bfin_dma@8", "di"),
+ SIC (0, 12, "bfin_dma@9", "di"),
+ SIC (0, 13, "bfin_dma@10", "di"),
+ SIC (0, 14, "bfin_dma@11", "di"),
+ SIC (0, 15, "bfin_can@0", "rx"),
+ SIC (0, 16, "bfin_can@0", "tx"),
+ SIC (0, 17, "bfin_dma@1", "di"),
+ SIC (0, 17, "bfin_gpio@7", "mask_a"),
+ SIC (0, 18, "bfin_dma@2", "di"),
+ SIC (0, 18, "bfin_gpio@7", "mask_b"),
+ SIC (0, 19, "bfin_gptimer@0", "stat"),
+ SIC (0, 20, "bfin_gptimer@1", "stat"),
+ SIC (0, 21, "bfin_gptimer@2", "stat"),
+ SIC (0, 22, "bfin_gptimer@3", "stat"),
+ SIC (0, 23, "bfin_gptimer@4", "stat"),
+ SIC (0, 24, "bfin_gptimer@5", "stat"),
+ SIC (0, 25, "bfin_gptimer@6", "stat"),
+ SIC (0, 26, "bfin_gptimer@7", "stat"),
+ SIC (0, 27, "bfin_gpio@5", "mask_a"),
+ SIC (0, 27, "bfin_gpio@6", "mask_a"),
+ SIC (0, 28, "bfin_gpio@6", "mask_b"),
+ SIC (0, 29, "bfin_dma@256", "di"), /* mdma0 */
+ SIC (0, 29, "bfin_dma@257", "di"), /* mdma0 */
+ SIC (0, 30, "bfin_dma@258", "di"), /* mdma1 */
+ SIC (0, 30, "bfin_dma@259", "di"), /* mdma1 */
+ SIC (0, 31, "bfin_wdog@0", "gpi"),
+ SIC (0, 31, "bfin_gpio@5", "mask_b"),
+};
+#define bf534_port bf537_port
+#define bf536_port bf537_port
#define bf538_chipid 0x27c4
#define bf539_chipid bf538_chipid
{ BFIN_MMR_DMAC1_BASE, 12, },
};
#define bf539_dmac bf538_dmac
+static const struct bfin_port_layout bf538_port[] =
+{
+ SIC (0, 0, "bfin_pll", "pll"),
+ SIC (0, 1, "bfin_dmac@0", "stat"),
+ SIC (0, 2, "bfin_ppi@0", "stat"),
+ SIC (0, 3, "bfin_sport@0", "stat"),
+ SIC (0, 4, "bfin_sport@1", "stat"),
+ SIC (0, 5, "bfin_spi@0", "stat"),
+ SIC (0, 6, "bfin_uart@0", "stat"),
+ SIC (0, 7, "bfin_rtc", "rtc"),
+ SIC (0, 8, "bfin_dma@0", "di"),
+ SIC (0, 9, "bfin_dma@1", "di"),
+ SIC (0, 10, "bfin_dma@2", "di"),
+ SIC (0, 11, "bfin_dma@3", "di"),
+ SIC (0, 12, "bfin_dma@4", "di"),
+ SIC (0, 13, "bfin_dma@5", "di"),
+ SIC (0, 14, "bfin_dma@6", "di"),
+ SIC (0, 15, "bfin_dma@7", "di"),
+ SIC (0, 16, "bfin_gptimer@0", "stat"),
+ SIC (0, 17, "bfin_gptimer@1", "stat"),
+ SIC (0, 18, "bfin_gptimer@2", "stat"),
+ SIC (0, 19, "bfin_gpio@5", "mask_a"),
+ SIC (0, 20, "bfin_gpio@5", "mask_b"),
+ SIC (0, 21, "bfin_dma@256", "di"), /* mdma0 */
+ SIC (0, 21, "bfin_dma@257", "di"), /* mdma0 */
+ SIC (0, 22, "bfin_dma@258", "di"), /* mdma1 */
+ SIC (0, 22, "bfin_dma@259", "di"), /* mdma1 */
+ SIC (0, 23, "bfin_wdog@0", "gpi"),
+ SIC (0, 24, "bfin_dmac@1", "stat"),
+ SIC (0, 25, "bfin_sport@2", "stat"),
+ SIC (0, 26, "bfin_sport@3", "stat"),
+/*SIC (0, 27, reserved),*/
+ SIC (0, 28, "bfin_spi@1", "stat"),
+ SIC (0, 29, "bfin_spi@2", "stat"),
+ SIC (0, 30, "bfin_uart@1", "stat"),
+ SIC (0, 31, "bfin_uart@2", "stat"),
+ SIC (1, 0, "bfin_can@0", "stat"),
+ SIC (1, 1, "bfin_dma@8", "di"),
+ SIC (1, 2, "bfin_dma@9", "di"),
+ SIC (1, 3, "bfin_dma@10", "di"),
+ SIC (1, 4, "bfin_dma@11", "di"),
+ SIC (1, 5, "bfin_dma@12", "di"),
+ SIC (1, 6, "bfin_dma@13", "di"),
+ SIC (1, 7, "bfin_dma@14", "di"),
+ SIC (1, 8, "bfin_dma@15", "di"),
+ SIC (1, 9, "bfin_dma@16", "di"),
+ SIC (1, 10, "bfin_dma@17", "di"),
+ SIC (1, 11, "bfin_dma@18", "di"),
+ SIC (1, 12, "bfin_dma@19", "di"),
+ SIC (1, 13, "bfin_twi@0", "stat"),
+ SIC (1, 14, "bfin_twi@1", "stat"),
+ SIC (1, 15, "bfin_can@0", "rx"),
+ SIC (1, 16, "bfin_can@0", "tx"),
+ SIC (1, 17, "bfin_dma@260", "di"), /* mdma2 */
+ SIC (1, 17, "bfin_dma@261", "di"), /* mdma2 */
+ SIC (1, 18, "bfin_dma@262", "di"), /* mdma3 */
+ SIC (1, 18, "bfin_dma@263", "di"), /* mdma3 */
+};
+#define bf539_port bf538_port
#define bf54x_chipid 0x27de
#define bf542_chipid bf54x_chipid
#define bf547_dmac bf54x_dmac
#define bf548_dmac bf54x_dmac
#define bf549_dmac bf54x_dmac
+static const struct bfin_port_layout bf54x_port[] =
+{
+ SIC (0, 0, "bfin_pll", "pll"),
+ SIC (0, 1, "bfin_dmac@0", "stat"),
+ SIC (0, 2, "bfin_eppi@0", "stat"),
+ SIC (0, 3, "bfin_sport@0", "stat"),
+ SIC (0, 4, "bfin_sport@1", "stat"),
+ SIC (0, 5, "bfin_spi@0", "stat"),
+ SIC (0, 6, "bfin_uart2@0", "stat"),
+ SIC (0, 7, "bfin_rtc", "rtc"),
+ SIC (0, 8, "bfin_dma@12", "di"),
+ SIC (0, 9, "bfin_dma@0", "di"),
+ SIC (0, 10, "bfin_dma@1", "di"),
+ SIC (0, 11, "bfin_dma@2", "di"),
+ SIC (0, 12, "bfin_dma@3", "di"),
+ SIC (0, 13, "bfin_dma@4", "di"),
+ SIC (0, 14, "bfin_dma@6", "di"),
+ SIC (0, 15, "bfin_dma@7", "di"),
+ SIC (0, 16, "bfin_gptimer@8", "stat"),
+ SIC (0, 17, "bfin_gptimer@9", "stat"),
+ SIC (0, 18, "bfin_gptimer@10", "stat"),
+ SIC (0, 19, "bfin_pint@0", "stat"),
+ SIC (0, 20, "bfin_pint@1", "stat"),
+ SIC (0, 21, "bfin_dma@256", "di"), /* mdma0 */
+ SIC (0, 21, "bfin_dma@257", "di"), /* mdma0 */
+ SIC (0, 22, "bfin_dma@258", "di"), /* mdma1 */
+ SIC (0, 22, "bfin_dma@259", "di"), /* mdma1 */
+ SIC (0, 23, "bfin_wdog@0", "gpi"),
+ SIC (0, 24, "bfin_dmac@1", "stat"),
+ SIC (0, 25, "bfin_sport@2", "stat"),
+ SIC (0, 26, "bfin_sport@3", "stat"),
+ SIC (0, 27, "bfin_mxvr", "data"),
+ SIC (0, 28, "bfin_spi@1", "stat"),
+ SIC (0, 29, "bfin_spi@2", "stat"),
+ SIC (0, 30, "bfin_uart2@1", "stat"),
+ SIC (0, 31, "bfin_uart2@2", "stat"),
+ SIC (1, 0, "bfin_can@0", "stat"),
+ SIC (1, 1, "bfin_dma@18", "di"),
+ SIC (1, 2, "bfin_dma@19", "di"),
+ SIC (1, 3, "bfin_dma@20", "di"),
+ SIC (1, 4, "bfin_dma@21", "di"),
+ SIC (1, 5, "bfin_dma@13", "di"),
+ SIC (1, 6, "bfin_dma@14", "di"),
+ SIC (1, 7, "bfin_dma@5", "di"),
+ SIC (1, 8, "bfin_dma@23", "di"),
+ SIC (1, 9, "bfin_dma@8", "di"),
+ SIC (1, 10, "bfin_dma@9", "di"),
+ SIC (1, 11, "bfin_dma@10", "di"),
+ SIC (1, 12, "bfin_dma@11", "di"),
+ SIC (1, 13, "bfin_twi@0", "stat"),
+ SIC (1, 14, "bfin_twi@1", "stat"),
+ SIC (1, 15, "bfin_can@0", "rx"),
+ SIC (1, 16, "bfin_can@0", "tx"),
+ SIC (1, 17, "bfin_dma@260", "di"), /* mdma2 */
+ SIC (1, 17, "bfin_dma@261", "di"), /* mdma2 */
+ SIC (1, 18, "bfin_dma@262", "di"), /* mdma3 */
+ SIC (1, 18, "bfin_dma@263", "di"), /* mdma3 */
+ SIC (1, 19, "bfin_mxvr", "stat"),
+ SIC (1, 20, "bfin_mxvr", "message"),
+ SIC (1, 21, "bfin_mxvr", "packet"),
+ SIC (1, 22, "bfin_eppi@1", "stat"),
+ SIC (1, 23, "bfin_eppi@2", "stat"),
+ SIC (1, 24, "bfin_uart2@3", "stat"),
+ SIC (1, 25, "bfin_hostdp", "stat"),
+/*SIC (1, 26, reserved),*/
+ SIC (1, 27, "bfin_pixc", "stat"),
+ SIC (1, 28, "bfin_nfc", "stat"),
+ SIC (1, 29, "bfin_atapi", "stat"),
+ SIC (1, 30, "bfin_can@1", "stat"),
+ SIC (1, 31, "bfin_dmar@0", "block"),
+ SIC (1, 31, "bfin_dmar@1", "block"),
+ SIC (1, 31, "bfin_dmar@0", "overflow"),
+ SIC (1, 31, "bfin_dmar@1", "overflow"),
+ SIC (2, 0, "bfin_dma@15", "di"),
+ SIC (2, 1, "bfin_dma@16", "di"),
+ SIC (2, 2, "bfin_dma@17", "di"),
+ SIC (2, 3, "bfin_dma@22", "di"),
+ SIC (2, 4, "bfin_counter@0", "stat"),
+ SIC (2, 5, "bfin_kpad@0", "stat"),
+ SIC (2, 6, "bfin_can@1", "rx"),
+ SIC (2, 7, "bfin_can@1", "tx"),
+ SIC (2, 8, "bfin_sdh", "mask0"),
+ SIC (2, 9, "bfin_sdh", "mask1"),
+/*SIC (2, 10, reserved),*/
+ SIC (2, 11, "bfin_usb", "int0"),
+ SIC (2, 12, "bfin_usb", "int1"),
+ SIC (2, 13, "bfin_usb", "int2"),
+ SIC (2, 14, "bfin_usb", "dma"),
+ SIC (2, 15, "bfin_otp", "stat"),
+/*SIC (2, 16, reserved),*/
+/*SIC (2, 17, reserved),*/
+/*SIC (2, 18, reserved),*/
+/*SIC (2, 19, reserved),*/
+/*SIC (2, 20, reserved),*/
+/*SIC (2, 21, reserved),*/
+ SIC (2, 22, "bfin_gptimer@0", "stat"),
+ SIC (2, 23, "bfin_gptimer@1", "stat"),
+ SIC (2, 24, "bfin_gptimer@2", "stat"),
+ SIC (2, 25, "bfin_gptimer@3", "stat"),
+ SIC (2, 26, "bfin_gptimer@4", "stat"),
+ SIC (2, 27, "bfin_gptimer@5", "stat"),
+ SIC (2, 28, "bfin_gptimer@6", "stat"),
+ SIC (2, 29, "bfin_gptimer@7", "stat"),
+ SIC (2, 30, "bfin_pint@2", "stat"),
+ SIC (2, 31, "bfin_pint@3", "stat"),
+};
+#define bf542_port bf54x_port
+#define bf544_port bf54x_port
+#define bf547_port bf54x_port
+#define bf548_port bf54x_port
+#define bf549_port bf54x_port
/* This is only Core A of course ... */
#define bf561_chipid 0x27bb
{ BFIN_MMR_DMAC1_BASE, 12, },
/* XXX: IMDMA: { 0xFFC01800, 4, }, */
};
+static const struct bfin_port_layout bf561_port[] =
+{
+ /* SIC0 */
+ SIC (0, 0, "bfin_pll", "pll"),
+/*SIC (0, 1, "bfin_dmac@0", "stat"),*/
+/*SIC (0, 2, "bfin_dmac@1", "stat"),*/
+/*SIC (0, 3, "bfin_imdmac", "stat"),*/
+ SIC (0, 4, "bfin_ppi@0", "stat"),
+ SIC (0, 5, "bfin_ppi@1", "stat"),
+ SIC (0, 6, "bfin_sport@0", "stat"),
+ SIC (0, 7, "bfin_sport@1", "stat"),
+ SIC (0, 8, "bfin_spi@0", "stat"),
+ SIC (0, 9, "bfin_uart@0", "stat"),
+/*SIC (0, 10, reserved),*/
+ SIC (0, 11, "bfin_dma@12", "di"),
+ SIC (0, 12, "bfin_dma@13", "di"),
+ SIC (0, 13, "bfin_dma@14", "di"),
+ SIC (0, 14, "bfin_dma@15", "di"),
+ SIC (0, 15, "bfin_dma@16", "di"),
+ SIC (0, 16, "bfin_dma@17", "di"),
+ SIC (0, 17, "bfin_dma@18", "di"),
+ SIC (0, 18, "bfin_dma@19", "di"),
+ SIC (0, 19, "bfin_dma@20", "di"),
+ SIC (0, 20, "bfin_dma@21", "di"),
+ SIC (0, 21, "bfin_dma@22", "di"),
+ SIC (0, 22, "bfin_dma@23", "di"),
+ SIC (0, 23, "bfin_dma@0", "di"),
+ SIC (0, 24, "bfin_dma@1", "di"),
+ SIC (0, 25, "bfin_dma@2", "di"),
+ SIC (0, 26, "bfin_dma@3", "di"),
+ SIC (0, 27, "bfin_dma@4", "di"),
+ SIC (0, 28, "bfin_dma@5", "di"),
+ SIC (0, 29, "bfin_dma@6", "di"),
+ SIC (0, 30, "bfin_dma@7", "di"),
+ SIC (0, 31, "bfin_dma@8", "di"),
+ SIC (1, 0, "bfin_dma@9", "di"),
+ SIC (1, 1, "bfin_dma@10", "di"),
+ SIC (1, 2, "bfin_dma@11", "di"),
+ SIC (1, 3, "bfin_gptimer@0", "stat"),
+ SIC (1, 4, "bfin_gptimer@1", "stat"),
+ SIC (1, 5, "bfin_gptimer@2", "stat"),
+ SIC (1, 6, "bfin_gptimer@3", "stat"),
+ SIC (1, 7, "bfin_gptimer@4", "stat"),
+ SIC (1, 8, "bfin_gptimer@5", "stat"),
+ SIC (1, 9, "bfin_gptimer@6", "stat"),
+ SIC (1, 10, "bfin_gptimer@7", "stat"),
+ SIC (1, 11, "bfin_gptimer@8", "stat"),
+ SIC (1, 12, "bfin_gptimer@9", "stat"),
+ SIC (1, 13, "bfin_gptimer@10", "stat"),
+ SIC (1, 14, "bfin_gptimer@11", "stat"),
+ SIC (1, 15, "bfin_gpio@5", "mask_a"),
+ SIC (1, 16, "bfin_gpio@5", "mask_b"),
+ SIC (1, 17, "bfin_gpio@6", "mask_a"),
+ SIC (1, 18, "bfin_gpio@6", "mask_b"),
+ SIC (1, 19, "bfin_gpio@7", "mask_a"),
+ SIC (1, 20, "bfin_gpio@7", "mask_b"),
+ SIC (1, 21, "bfin_dma@256", "di"), /* mdma0 */
+ SIC (1, 21, "bfin_dma@257", "di"), /* mdma0 */
+ SIC (1, 22, "bfin_dma@258", "di"), /* mdma1 */
+ SIC (1, 22, "bfin_dma@259", "di"), /* mdma1 */
+ SIC (1, 23, "bfin_dma@260", "di"), /* mdma2 */
+ SIC (1, 23, "bfin_dma@261", "di"), /* mdma2 */
+ SIC (1, 24, "bfin_dma@262", "di"), /* mdma3 */
+ SIC (1, 24, "bfin_dma@263", "di"), /* mdma3 */
+ SIC (1, 25, "bfin_imdma@0", "di"),
+ SIC (1, 26, "bfin_imdma@1", "di"),
+ SIC (1, 27, "bfin_wdog@0", "gpi"),
+ SIC (1, 27, "bfin_wdog@1", "gpi"),
+/*SIC (1, 28, reserved),*/
+/*SIC (1, 29, reserved),*/
+ SIC (1, 30, "bfin_sic", "sup_irq@0"),
+ SIC (1, 31, "bfin_sic", "sup_irq@1"),
+};
#define bf592_chipid 0x20cb
static const struct bfin_memory_layout bf592_mem[] =
start right after the dma channels ... */
{ BFIN_MMR_DMAC0_BASE, 12, },
};
+static const struct bfin_port_layout bf592_port[] =
+{
+ SIC (0, 0, "bfin_pll", "pll"),
+/*SIC (0, 1, "bfin_dmac@0", "stat"),*/
+ SIC (0, 2, "bfin_ppi@0", "stat"),
+ SIC (0, 3, "bfin_sport@0", "stat"),
+ SIC (0, 4, "bfin_sport@1", "stat"),
+ SIC (0, 5, "bfin_spi@0", "stat"),
+ SIC (0, 6, "bfin_spi@1", "stat"),
+ SIC (0, 7, "bfin_uart@0", "stat"),
+ SIC (0, 8, "bfin_dma@0", "di"),
+ SIC (0, 9, "bfin_dma@1", "di"),
+ SIC (0, 10, "bfin_dma@2", "di"),
+ SIC (0, 11, "bfin_dma@3", "di"),
+ SIC (0, 12, "bfin_dma@4", "di"),
+ SIC (0, 13, "bfin_dma@5", "di"),
+ SIC (0, 14, "bfin_dma@6", "di"),
+ SIC (0, 15, "bfin_dma@7", "di"),
+ SIC (0, 16, "bfin_dma@8", "di"),
+ SIC (0, 17, "bfin_gpio@5", "mask_a"),
+ SIC (0, 18, "bfin_gpio@5", "mask_b"),
+ SIC (0, 19, "bfin_gptimer@0", "stat"),
+ SIC (0, 20, "bfin_gptimer@1", "stat"),
+ SIC (0, 21, "bfin_gptimer@2", "stat"),
+ SIC (0, 22, "bfin_gpio@6", "mask_a"),
+ SIC (0, 23, "bfin_gpio@6", "mask_b"),
+ SIC (0, 24, "bfin_twi@0", "stat"),
+/* XXX: 25 - 28 are supposed to be reserved; see comment in machs.c:bf592_dmac[] */
+ SIC (0, 25, "bfin_dma@9", "di"),
+ SIC (0, 26, "bfin_dma@10", "di"),
+ SIC (0, 27, "bfin_dma@11", "di"),
+ SIC (0, 28, "bfin_dma@12", "di"),
+/*SIC (0, 25, reserved),*/
+/*SIC (0, 26, reserved),*/
+/*SIC (0, 27, reserved),*/
+/*SIC (0, 28, reserved),*/
+ SIC (0, 29, "bfin_dma@256", "di"), /* mdma0 */
+ SIC (0, 29, "bfin_dma@257", "di"), /* mdma0 */
+ SIC (0, 30, "bfin_dma@258", "di"), /* mdma1 */
+ SIC (0, 30, "bfin_dma@259", "di"), /* mdma1 */
+ SIC (0, 31, "bfin_wdog", "gpi"),
+};
static const struct bfin_model_data bfin_model_data[] =
{
bf##n##_mem , ARRAY_SIZE (bf##n##_mem ), \
bf##n##_dev , ARRAY_SIZE (bf##n##_dev ), \
bf##n##_dmac, ARRAY_SIZE (bf##n##_dmac), \
+ bf##n##_port, ARRAY_SIZE (bf##n##_port), \
},
#include "proc_list.def"
#undef P
CORE_DEVICE (wp, WP),
};
+static void
+dv_bfin_hw_port_parse (SIM_DESC sd, const struct bfin_model_data *mdata,
+ const char *dev)
+{
+ size_t i;
+ const char *sdev;
+
+ sdev = strchr (dev, '/');
+ if (sdev)
+ ++sdev;
+ else
+ sdev = dev;
+
+ for (i = 0; i < mdata->port_count; ++i)
+ {
+ const struct bfin_port_layout *port = &mdata->port[i];
+
+ /* There might be more than one mapping. */
+ if (!strcmp (sdev, port->src))
+ sim_hw_parse (sd, "/core/%s > %s %s /core/%s", dev,
+ port->src_port, port->dst_port, port->dst);
+ }
+}
+
#define dv_bfin_hw_parse(sd, dv, DV) \
do { \
bu32 base = BFIN_MMR_##DV##_BASE; \
bu32 size = BFIN_MMR_##DV##_SIZE; \
sim_hw_parse (sd, "/core/bfin_"#dv"/reg %#x %i", base, size); \
sim_hw_parse (sd, "/core/bfin_"#dv"/type %i", mdata->model_num); \
+ dv_bfin_hw_port_parse (sd, mdata, "bfin_"#dv); \
} while (0)
static void
sim_hw_parse (sd, "/core/bfin_sic > ivg%i ivg%i /core/bfin_cec", i, i);
dv_bfin_hw_parse (sd, pll, PLL);
- sim_hw_parse (sd, "/core/bfin_pll > pll pll /core/bfin_sic");
dma_chan = 0;
for (i = 0; i < mdata->dmac_count; ++i)
/* Hook up the non-mdma channels. */
for (j = 0; j < dmac->dma_count; ++j)
{
- sim_hw_parse (sd, "/core/bfin_dmac@%u/bfin_dma@%u/reg %#x %i", i,
- dma_chan, dmac->base + j * BFIN_MMR_DMA_SIZE,
- BFIN_MMR_DMA_SIZE);
+ char dev[64];
- /* Could route these into the bfin_dmac and let that
- forward it to the SIC, but not much value. */
- sim_hw_parse (sd, "/core/bfin_dmac@%u/bfin_dma@%u > di dma@%u /core/bfin_sic",
- i, dma_chan, dma_chan);
+ sprintf (dev, "bfin_dmac@%u/bfin_dma@%u", i, dma_chan);
+ sim_hw_parse (sd, "/core/%s/reg %#x %i", dev,
+ dmac->base + j * BFIN_MMR_DMA_SIZE, BFIN_MMR_DMA_SIZE);
+ dv_bfin_hw_port_parse (sd, mdata, dev);
++dma_chan;
}
/* Hook up the mdma channels -- assume every DMAC has 4. */
for (j = 0; j < 4; ++j)
{
- sim_hw_parse (sd, "/core/bfin_dmac@%u/bfin_dma@%u/reg %#x %i",
- i, j + BFIN_DMAC_MDMA_BASE,
+ char dev[64];
+
+ sprintf (dev, "bfin_dmac@%u/bfin_dma@%u", i, j + BFIN_DMAC_MDMA_BASE);
+ sim_hw_parse (sd, "/core/%s/reg %#x %i", dev,
dmac->base + (j + dmac->dma_count) * BFIN_MMR_DMA_SIZE,
BFIN_MMR_DMA_SIZE);
- sim_hw_parse (sd, "/core/bfin_dmac@%u/bfin_dma@%u > di mdma@%u /core/bfin_sic",
- i, j + BFIN_DMAC_MDMA_BASE, (2 * i) + (j / 2));
+ dv_bfin_hw_port_parse (sd, mdata, dev);
}
}
for (i = 0; i < mdata->dev_count; ++i)
{
const struct bfin_dev_layout *dev = &mdata->dev[i];
+
sim_hw_parse (sd, "/core/%s/reg %#x %i", dev->dev, dev->base, dev->len);
sim_hw_parse (sd, "/core/%s/type %i", dev->dev, mdata->model_num);
if (strchr (dev->dev, '/'))
continue;
+ dv_bfin_hw_port_parse (sd, mdata, dev->dev);
+
if (!strncmp (dev->dev, "bfin_uart", 9)
|| !strncmp (dev->dev, "bfin_emac", 9)
|| !strncmp (dev->dev, "bfin_sport", 10))
const char *sint = dev->dev + 5;
sim_hw_parse (sd, "/core/%s > tx %s_tx /core/bfin_dmac@%u", dev->dev, sint, dev->dmac);
sim_hw_parse (sd, "/core/%s > rx %s_rx /core/bfin_dmac@%u", dev->dev, sint, dev->dmac);
- sim_hw_parse (sd, "/core/%s > stat %s_stat /core/bfin_sic", dev->dev, sint);
- }
- else if (!strncmp (dev->dev, "bfin_gptimer", 12)
- || !strncmp (dev->dev, "bfin_ppi", 8)
- || !strncmp (dev->dev, "bfin_spi", 8)
- || !strncmp (dev->dev, "bfin_twi", 8))
- {
- const char *sint = dev->dev + 5;
- sim_hw_parse (sd, "/core/%s > stat %s /core/bfin_sic", dev->dev, sint);
- }
- else if (!strncmp (dev->dev, "bfin_rtc", 8))
- {
- const char *sint = dev->dev + 5;
- sim_hw_parse (sd, "/core/%s > %s %s /core/bfin_sic", dev->dev, sint, sint);
}
else if (!strncmp (dev->dev, "bfin_wdog", 9))
{
sim_hw_parse (sd, "/core/%s > reset rst /core/bfin_cec", dev->dev);
sim_hw_parse (sd, "/core/%s > nmi nmi /core/bfin_cec", dev->dev);
- sim_hw_parse (sd, "/core/%s > gpi wdog /core/bfin_sic", dev->dev);
- }
- else if (!strncmp (dev->dev, "bfin_gpio", 9))
- {
- char port = 'a' + strtol(&dev->dev[10], NULL, 0);
- sim_hw_parse (sd, "/core/%s > mask_a port%c_irq_a /core/bfin_sic",
- dev->dev, port);
- sim_hw_parse (sd, "/core/%s > mask_b port%c_irq_b /core/bfin_sic",
- dev->dev, port);
}
}
projects / binutils-gdb.git / commitdiff