mibuild: add support for libraries, move .replace("\\", "/") to generic_platform...

We need to support libraries when Migen is used as a wrapper on large VHDL designs using libraries.

diff --git a/mibuild/altera/quartus.py b/mibuild/altera/quartus.py
index 09fbc96dc05f819333b0d6986bae196c2e4e093f..9e29f6f3f8c4c26ebaafbfba6bcad1a21e9c5198 100644 (file)
--- a/mibuild/altera/quartus.py
+++ b/mibuild/altera/quartus.py
@@ -47,14 +47,14 @@ def _build_qsf(named_sc, named_pc):
 
 def _build_files(device, sources, vincpaths, named_sc, named_pc, build_name):
     qsf_contents = ""
-    for filename, language in sources:
+    for filename, language, library in sources:
         # Enforce use of SystemVerilog (Quartus does not support global parameters in Verilog)
         if language == "verilog":
             language = "systemverilog"
-        qsf_contents += "set_global_assignment -name " + language.upper() + "_FILE " + filename.replace("\\", "/") + "\n"
+        qsf_contents += "set_global_assignment -name " + language.upper() + "_FILE " + filename + " -library " + library + " \n"
 
     for path in vincpaths:
-        qsf_contents += "set_global_assignment -name SEARCH_PATH " + path.replace("\\", "/") + "\n"
+        qsf_contents += "set_global_assignment -name SEARCH_PATH " + path + "\n"
 
     qsf_contents += _build_qsf(named_sc, named_pc)
     qsf_contents += "set_global_assignment -name DEVICE " + device
@@ -92,7 +92,7 @@ class AlteraQuartusToolchain:
         named_sc, named_pc = platform.resolve_signals(v_output.ns)
         v_file = build_name + ".v"
         v_output.write(v_file)
-        sources = platform.sources | {(v_file, "verilog")}
+        sources = platform.sources | {(v_file, "verilog", "work")}
         _build_files(platform.device, sources, platform.verilog_include_paths, named_sc, named_pc, build_name)
         if run:
             _run_quartus(build_name, quartus_path)

diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py
index 91a3937b2cc307fd5c60f347b98b70b95572fc54..0e50e11a121f5d8d510a8aa4b6a1037b34176721 100644 (file)
--- a/mibuild/generic_platform.py
+++ b/mibuild/generic_platform.py
@@ -237,19 +237,23 @@ class GenericPlatform:
             except ConstraintError:
                 pass
 
-    def add_source(self, filename, language=None):
+    def add_source(self, filename, language=None, library=None):
         if language is None:
             language = tools.language_by_filename(filename)
         if language is None:
             language = "verilog"  # default to Verilog
+        if library is None:
+            library = "work"  # default to work
         filename = os.path.abspath(filename)
-        self.sources.add((filename, language))
+        if sys.platform == "win32" or sys.platform == "cygwin":
+            filename = filename.replace("\\", "/")
+        self.sources.add((filename, language, library))
 
-    def add_sources(self, path, *filenames, language=None):
+    def add_sources(self, path, *filenames, language=None, library=None):
         for f in filenames:
-            self.add_source(os.path.join(path, f), language)
+            self.add_source(os.path.join(path, f), language, library)
 
-    def add_source_dir(self, path, recursive=True):
+    def add_source_dir(self, path, recursive=True, library=None):
         dir_files = []
         if recursive:
             for root, dirs, files in os.walk(path):
@@ -262,10 +266,13 @@ class GenericPlatform:
         for filename in dir_files:
             language = tools.language_by_filename(filename)
             if language is not None:
-                self.add_source(filename, language)
+                self.add_source(filename, language, library)
 
     def add_verilog_include_path(self, path):
-        self.verilog_include_paths.add(os.path.abspath(path))
+        path = os.path.abspath(path)
+        if sys.platform == "win32" or sys.platform == "cygwin":
+            path = path.replace("\\", "/")
+        self.verilog_include_paths.add(path)
 
     def resolve_signals(self, vns):
         # resolve signal names in constraints

diff --git a/mibuild/lattice/diamond.py b/mibuild/lattice/diamond.py
index a8a30556ce79104a53b4238d858401f7925df51e..0b9f486cc8586a99269fcd041507edc87b8f0c95 100644 (file)
--- a/mibuild/lattice/diamond.py
+++ b/mibuild/lattice/diamond.py
@@ -47,9 +47,9 @@ def _build_files(device, sources, vincpaths, build_name):
     tcl = []
     tcl.append("prj_project new -name \"{}\" -impl \"implementation\" -dev {} -synthesis \"synplify\"".format(build_name, device))
     for path in vincpaths:
-        tcl.append("prj_impl option {include path} {\"" + path.replace("\\", "/") + "\"}")
-    for filename, language in sources:
-        tcl.append("prj_src add \"" + filename.replace("\\", "/") + "\"")
+        tcl.append("prj_impl option {include path} {\"" + path + "\"}")
+    for filename, language, library in sources:
+        tcl.append("prj_src add \"" + filename + "\" -work " + library)
     tcl.append("prj_run Synthesis -impl implementation -forceOne")
     tcl.append("prj_run Translate -impl implementation")
     tcl.append("prj_run Map -impl implementation")
@@ -67,7 +67,7 @@ def _run_diamond(build_name, source, ver=None):
         r = subprocess.call([build_script_file])
         shutil.copy(os.path.join("implementation", build_name + "_implementation.bit"), build_name + ".bit")
     else:
-        raise NotImplementedError()
+        raise NotImplementedError
 
     if r != 0:
         raise OSError("Subprocess failed")
@@ -87,7 +87,7 @@ class LatticeDiamondToolchain:
         named_sc, named_pc = platform.resolve_signals(v_output.ns)
         v_file = build_name + ".v"
         v_output.write(v_file)
-        sources = platform.sources | {(v_file, "verilog")}
+        sources = platform.sources | {(v_file, "verilog", "work")}
         _build_files(platform.device, sources, platform.verilog_include_paths, build_name)
 
         tools.write_to_file(build_name + ".lpf", _build_lpf(named_sc, named_pc))

diff --git a/mibuild/xilinx/ise.py b/mibuild/xilinx/ise.py
index be4405cedacb1b86a85eca7df184db341ec6c2ed..5f89c416946582cc1cb725fe406fa0f7ef8aca9d 100644 (file)
--- a/mibuild/xilinx/ise.py
+++ b/mibuild/xilinx/ise.py
@@ -48,8 +48,8 @@ def _build_ucf(named_sc, named_pc):
 
 def _build_xst_files(device, sources, vincpaths, build_name, xst_opt):
     prj_contents = ""
-    for filename, language in sources:
-        prj_contents += language + " work " + filename + "\n"
+    for filename, language, library in sources:
+        prj_contents += language + " " + library + " " + filename + "\n"
     tools.write_to_file(build_name + ".prj", prj_contents)
 
     xst_contents = """run
@@ -159,7 +159,7 @@ class XilinxISEToolchain:
             named_sc, named_pc = platform.resolve_signals(vns)
             v_file = build_name + ".v"
             v_output.write(v_file)
-            sources = platform.sources | {(v_file, "verilog")}
+            sources = platform.sources | {(v_file, "verilog", "work")}
             if mode == "xst":
                 _build_xst_files(platform.device, sources, platform.verilog_include_paths, build_name, self.xst_opt)
                 isemode = "xst"

diff --git a/mibuild/xilinx/vivado.py b/mibuild/xilinx/vivado.py
index 24ea9d56ec346704cf4ccc90e88effd2429b650e..8f732a4982285cad47e0b272a09a38b6ee8e702b 100644 (file)
--- a/mibuild/xilinx/vivado.py
+++ b/mibuild/xilinx/vivado.py
@@ -81,8 +81,9 @@ class XilinxVivadoToolchain:
 
     def _build_batch(self, platform, sources, build_name):
         tcl = []
-        for filename, language in sources:
-            tcl.append("add_files " + filename.replace("\\", "/"))
+        for filename, language, library in sources:
+            tcl.append("add_files " + filename)
+            tcl.append("set_property library {} [get_files {}]".format(library, filename))
 
         tcl.append("read_xdc {}.xdc".format(build_name))
         tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands)
@@ -122,7 +123,7 @@ class XilinxVivadoToolchain:
         named_sc, named_pc = platform.resolve_signals(v_output.ns)
         v_file = build_name + ".v"
         v_output.write(v_file)
-        sources = platform.sources | {(v_file, "verilog")}
+        sources = platform.sources | {(v_file, "verilog", "work")}
         self._build_batch(platform, sources, build_name)
         tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc))
         if run: