\f
;; Recognizers for btst instructions.
+;; Coldfire/5200 only allows "<Q>" type addresses when the bit position is
+;; specified as a constant, so we must disable all patterns that may extract
+;; from a MEM at a constant bit position if we can't use this as a constraint.
+
(define_insn ""
[(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
(const_int 1)
(minus:SI (const_int 7)
(match_operand:SI 1 "general_operand" "di"))))]
- ""
+ "!TARGET_5200"
+ "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
+
+;; This is the same as the above pattern except for the constraints. The 'i'
+;; has been deleted.
+
+(define_insn ""
+ [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
+ (const_int 1)
+ (minus:SI (const_int 7)
+ (match_operand:SI 1 "general_operand" "d"))))]
+ "TARGET_5200"
"* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
(define_insn ""
[(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
(const_int 1)
(match_operand:SI 1 "const_int_operand" "n")))]
- "(unsigned) INTVAL (operands[1]) < 8"
+ "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_5200"
"*
{
operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1]));
[(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
(const_int 1)
(match_operand:SI 1 "const_int_operand" "n")))]
- ""
+ "!TARGET_5200"
+ "*
+{
+ if (GET_CODE (operands[0]) == MEM)
+ {
+ operands[0] = adj_offsettable_operand (operands[0],
+ INTVAL (operands[1]) / 8);
+ operands[1] = gen_rtx (CONST_INT, VOIDmode,
+ 7 - INTVAL (operands[1]) % 8);
+ return output_btst (operands, operands[1], operands[0], insn, 7);
+ }
+ operands[1] = gen_rtx (CONST_INT, VOIDmode,
+ 31 - INTVAL (operands[1]));
+ return output_btst (operands, operands[1], operands[0], insn, 31);
+}")
+
+;; This is the same as the above pattern except for the constraints.
+;; The 'o' has been replaced with 'Q'.
+
+(define_insn ""
+ [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ")
+ (const_int 1)
+ (match_operand:SI 1 "const_int_operand" "n")))]
+ "TARGET_5200"
"*
{
if (GET_CODE (operands[0]) == MEM)