return 0;
}
+uint64_t AstNode::asInt(bool is_signed)
+{
+ if (type == AST_CONSTANT)
+ {
+ RTLIL::Const v = bitsAsConst(64, is_signed);
+ uint64_t ret = 0;
+
+ for (int i = 0; i < 64; i++)
+ if (v.bits.at(i) == RTLIL::State::S1)
+ ret |= uint64_t(1) << i;
+
+ return ret;
+ }
+
+ if (type == AST_REALVALUE)
+ return realvalue;
+
+ log_abort();
+}
+
double AstNode::asReal(bool is_signed)
{
- if (type == AST_CONSTANT) {
+ if (type == AST_CONSTANT)
+ {
RTLIL::Const val(bits);
bool is_negative = is_signed && val.bits.back() == RTLIL::State::S1;
RTLIL::Const bitsAsConst(int width = -1);
RTLIL::Const asAttrConst();
RTLIL::Const asParaConst();
+ uint64_t asInt(bool is_signed);
bool bits_only_01();
bool asBool();
if (argtypes[i] == "real" || argtypes[i] == "shortreal")
log(" arg %d (%s): %f\n", i, argtypes[i].c_str(), args[i]->asReal(args[i]->is_signed));
else
- log(" arg %d (%s): %d\n", i, argtypes[i].c_str(), args[i]->bitsAsConst().as_int());
+ log(" arg %d (%s): %lld\n", i, argtypes[i].c_str(), (long long)args[i]->asInt(args[i]->is_signed));
if (rtype == "real" || rtype == "shortreal") {
newNode = new AstNode(AST_REALVALUE);