Update switch to nMigen syntax

diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py
index ad4b7c9cf62ca49baabf731a7801e10bd728d0fc..9a3818d6bfb0734dfdb61f97491e3d7568478e2b 100644 (file)
--- a/gram/phy/ecp5ddrphy.py
+++ b/gram/phy/ecp5ddrphy.py
@@ -264,11 +264,11 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
                     m.d.sync += dqs_bitslip.eq(0)
                 with m.Elif(self._rdly_dq_bitslip.w_stb):
                     m.d.sync += dqs_bitslip.eq(dqs_bitslip + 1)
-            dqs_cases = {}
-            for j, b in enumerate(range(-2, 2)):
-                dqs_cases[j] = dqs_read.eq(
-                    rddata_en[cl_sys_latency + b:cl_sys_latency + b + 2] != 0)
-            m.d.sync += Case(dqs_bitslip, dqs_cases)
+            with m.Switch(dqs_bitslip):
+                for j, b in enumerate(range(-2, 2)):
+                    with m.Case(j):
+                        m.d.sync += dqs_read.eq(rddata_en[cl_sys_latency + b:cl_sys_latency + b + 2] != 0)
+
             m.submodules += Instance("DQSBUFM",
                                      p_DQS_LI_DEL_ADJ="MINUS",
                                      p_DQS_LI_DEL_VAL=1,