- # Add subproject to our running list
-
- subprojects="$subprojects hwacha"
-
- # Process the subproject appropriately. If enabled add it to the
- # $enabled_subprojects running shell variable, set a
- # SUBPROJECT_ENABLED C define, and include the appropriate
- # 'subproject.ac'.
-
-
- { $as_echo "$as_me:${as_lineno-$LINENO}: configuring default subproject : hwacha" >&5
-$as_echo "$as_me: configuring default subproject : hwacha" >&6;}
- ac_config_files="$ac_config_files hwacha.mk:hwacha/hwacha.mk.in"
-
- enable_hwacha_sproj="yes"
- subprojects_enabled="$subprojects_enabled hwacha"
-
-$as_echo "#define HWACHA_ENABLED /**/" >>confdefs.h
-
-
-
-
-
-
- # Determine if this is a required or an optional subproject
-
-
-
- # Determine if there is a group with the same name
-
-
-
- # Create variations of the subproject name suitable for use as a CPP
- # enabled define, a shell enabled variable, and a shell function
-
-
-
-
-
-
-
-
-
-
-
# Add subproject to our running list
subprojects="$subprojects dummy_rocc"
ac_config_files="$ac_config_files riscv-riscv.pc"
-ac_config_files="$ac_config_files riscv-hwacha.pc"
-
ac_config_files="$ac_config_files riscv-softfloat.pc"
ac_config_files="$ac_config_files riscv-dummy_rocc.pc"
do
case $ac_config_target in
"riscv.mk") CONFIG_FILES="$CONFIG_FILES riscv.mk:riscv/riscv.mk.in" ;;
- "hwacha.mk") CONFIG_FILES="$CONFIG_FILES hwacha.mk:hwacha/hwacha.mk.in" ;;
"dummy_rocc.mk") CONFIG_FILES="$CONFIG_FILES dummy_rocc.mk:dummy_rocc/dummy_rocc.mk.in" ;;
"softfloat.mk") CONFIG_FILES="$CONFIG_FILES softfloat.mk:softfloat/softfloat.mk.in" ;;
"spike_main.mk") CONFIG_FILES="$CONFIG_FILES spike_main.mk:spike_main/spike_main.mk.in" ;;
"Makefile") CONFIG_FILES="$CONFIG_FILES Makefile" ;;
"riscv-spike.pc") CONFIG_FILES="$CONFIG_FILES riscv-spike.pc" ;;
"riscv-riscv.pc") CONFIG_FILES="$CONFIG_FILES riscv-riscv.pc" ;;
- "riscv-hwacha.pc") CONFIG_FILES="$CONFIG_FILES riscv-hwacha.pc" ;;
"riscv-softfloat.pc") CONFIG_FILES="$CONFIG_FILES riscv-softfloat.pc" ;;
"riscv-dummy_rocc.pc") CONFIG_FILES="$CONFIG_FILES riscv-dummy_rocc.pc" ;;
"riscv-spike_main.pc") CONFIG_FILES="$CONFIG_FILES riscv-spike_main.pc" ;;
# The '*' suffix indicates an optional subproject. The '**' suffix
# indicates an optional subproject which is also the name of a group.
-MCPPBS_SUBPROJECTS([ riscv, hwacha, dummy_rocc, softfloat, spike_main ])
+MCPPBS_SUBPROJECTS([ riscv, dummy_rocc, softfloat, spike_main ])
#-------------------------------------------------------------------------
# MCPPBS subproject groups
AC_CONFIG_FILES([Makefile])
AC_CONFIG_FILES([riscv-spike.pc])
AC_CONFIG_FILES([riscv-riscv.pc])
-AC_CONFIG_FILES([riscv-hwacha.pc])
AC_CONFIG_FILES([riscv-softfloat.pc])
AC_CONFIG_FILES([riscv-dummy_rocc.pc])
AC_CONFIG_FILES([riscv-spike_main.pc])
+++ /dev/null
-This directory contains work in progress on Hwacha, a data-parallel
-accelerator.
+++ /dev/null
-#include "cvt16.h"
-
-#define H_BIAS (UINT16_C(0xf))
-#define H_F_MASK (UINT16_C(0x03FF))
-#define H_E_MASK (UINT16_C(0x7C00))
-#define H_E_SHIFT (10)
-#define H_S_MASK (UINT16_C(0x8000))
-
-#define H_QNAN (H_F_MASK)
-
-#define S_BIAS (UINT32_C(0x7F))
-#define S_F_MASK (UINT32_C(0x007fffff))
-#define S_E_MASK (UINT32_C(0x7f800000))
-#define S_E_SHIFT (23)
-#define S_S_MASK (UINT32_C(0x80000000))
-
-#define S_QNAN (S_F_MASK)
-
-#define PAD (S_E_SHIFT - H_E_SHIFT)
-
-uint_fast32_t cvt_hs(uint_fast16_t x)
-{
-#define MSB (UINT32_C(0x00800000))
- uint_fast32_t frac, exp, sign;
- frac = (x & H_F_MASK) << PAD;
- exp = (x & H_E_MASK);
- sign = (x & H_S_MASK);
-
- switch (exp) {
- case 0:
- if (frac) { /* Denormal */
- exp = S_BIAS - 14;
- /* Adjust fraction for implicit leading 1-bit */
- for (; !(frac & MSB); frac <<= 1, exp--);
- frac &= ~(MSB);
- exp <<= S_E_SHIFT;
- }
- break;
-
- case H_E_MASK: /* Infinity and NaN */
- exp = S_E_MASK;
- if (frac) { /* Set padding bits for NaN */
- frac |= (1 << PAD) - 1;
- }
- break;
- default:
- exp += (S_BIAS - H_BIAS) << H_E_SHIFT; /* Re-bias */
- exp <<= PAD;
- }
- return (sign << 16) | exp | frac;
-#undef MSB
-}
-
-enum riscv_rm {
- RNE = 0, /* Round to nearest; ties to even */
- RTZ = 1, /* Round towards zero (truncate) */
- RDN = 2, /* Round towards negative infinity (down) */
- RUP = 3, /* Round towards positive infinity (up) */
- RMM = 4, /* Round to nearest; ties to max magnitude */
-};
-
-/*
- * LSB : frac[13]
- * Guard bit (G): frac[12]
- * Round bit (R): frac[11]
- * Sticky bit (S): OR of frac[10..0]
- *
- * RTZ:
- * truncate
- * RUP:
- * 000 : exact
- * else : round up
- * RDN:
- * 000 : exact
- * else : round down
- * RNE:
- * 0xx : round down
- * 100 : tie; round up if LSB is 1
- * 101 : round up
- * 110 : round up
- * 111 : round up
- */
-uint_fast16_t cvt_sh(uint_fast32_t x, int rm)
-{
-#define MSB UINT16_C(0x0400)
- uint_fast32_t frac, exp, sign;
- int e;
- sign = (x & S_S_MASK) >> 16;
- exp = (x & S_E_MASK);
- if (exp && exp != S_E_MASK) {
- int inc;
- inc = 0;
- switch (rm) {
- case RNE:
- /* Round up if G is set and either R, S,
- or the bit before G is non-zero */
- inc = (x & 0x1000) && (x & 0x2fff);
- break;
- case RUP:
- inc = ((x & 0x1fff) != 0) && (!sign);
- break;
- case RDN:
- inc = ((x & 0x1fff) != 0) && sign;
- break;
- }
- x += inc << PAD;
- exp = (x & S_E_MASK);
- }
- frac = (x & S_F_MASK) >> PAD;
-
- e = (exp >> S_E_SHIFT) - S_BIAS;
- if (e < -24) { /* Round to zero */
- return sign;
- } else if (e < -14) { /* Denormal */
- frac = (frac | MSB) >> (-e - 14);
- return sign | frac;
- } else if (e < 16) {
- exp = (e + H_BIAS) << H_E_SHIFT;
- } else if (e < 127) { /* Round to infinity */
- exp = H_E_MASK;
- frac = 0;
- } else {
- /* Infinity and NaN */
- }
- return sign | exp | frac;
-#undef MSB
-}
-
+++ /dev/null
-#ifndef _CVT16_H
-#define _CVT16_H
-
-#include <cstdint>
-
-extern uint_fast32_t cvt_hs(uint_fast16_t);
-extern uint_fast16_t cvt_sh(uint_fast32_t, int);
-
-#endif
+++ /dev/null
-#ifndef _DECODE_HWACHA_H
-#define _DECODE_HWACHA_H
-
-#include "hwacha.h"
-#include "hwacha_xcpt.h"
-#include "mmu.h"
-
-#define XS1 (xs1)
-#define XS2 (xs2)
-#define WRITE_XRD(value) (xd = value)
-
-#define NXPR (h->get_ct_state()->nxpr)
-#define NFPR (h->get_ct_state()->nfpr)
-#define MAXVL (h->get_ct_state()->maxvl)
-#define VL (h->get_ct_state()->vl)
-#define UTIDX (h->get_ct_state()->count)
-#define PREC (h->get_ct_state()->prec)
-#define VF_PC (h->get_ct_state()->vf_pc)
-#define WRITE_NXPR(nxprnext) (h->get_ct_state()->nxpr = (nxprnext))
-#define WRITE_NFPR(nfprnext) (h->get_ct_state()->nfpr = (nfprnext))
-#define WRITE_MAXVL(maxvlnext) (h->get_ct_state()->maxvl = (maxvlnext))
-#define WRITE_VL(vlnext) (h->get_ct_state()->vl = (vlnext))
-#define WRITE_UTIDX(value) (h->get_ct_state()->count = (value))
-#define WRITE_VF_PC(pcnext) (h->get_ct_state()->vf_pc = (pcnext))
-#define WRITE_PREC(precision) (h->get_ct_state()->prec = (precision))
-
-#define INSN_RS1 (insn.rs1())
-#define INSN_RS2 (insn.rs2())
-#define INSN_RS3 (insn.rs3())
-#define INSN_RD (insn.rd())
-#define INSN_SEG (((reg_t)insn.i_imm() >> 9)+1)
-
-static inline reg_t read_xpr(hwacha_t* h, insn_t insn, uint32_t idx, size_t src)
-{
- if (src >= h->get_ct_state()->nxpr)
- h->take_exception(HWACHA_CAUSE_TVEC_ILLEGAL_REGID, uint32_t(insn.bits()));
- return (h->get_ut_state(idx)->XPR[src]);
-}
-
-static inline void write_xpr(hwacha_t* h, insn_t insn, uint32_t idx, size_t dst, reg_t value)
-{
- if (dst >= h->get_ct_state()->nxpr)
- h->take_exception(HWACHA_CAUSE_TVEC_ILLEGAL_REGID, uint32_t(insn.bits()));
- h->get_ut_state(idx)->XPR.write(dst, value);
-}
-
-#define UT_READ_XPR(idx, src) read_xpr(h, insn, idx, src)
-#define UT_WRITE_XPR(idx, dst, value) write_xpr(h, insn, idx, dst, value)
-#define UT_RS1(idx) (UT_READ_XPR(idx, INSN_RS1))
-#define UT_RS2(idx) (UT_READ_XPR(idx, INSN_RS2))
-#define UT_WRITE_RD(idx, value) (UT_WRITE_XPR(idx, INSN_RD, value))
-
-static inline reg_t read_fpr(hwacha_t* h, insn_t insn, uint32_t idx, size_t src)
-{
- if (src >= h->get_ct_state()->nfpr)
- h->take_exception(HWACHA_CAUSE_TVEC_ILLEGAL_REGID, uint32_t(insn.bits()));
- return (h->get_ut_state(idx)->FPR[src]);
-}
-
-static inline void write_fpr(hwacha_t* h, insn_t insn, uint32_t idx, size_t dst, reg_t value)
-{
- if (dst >= h->get_ct_state()->nfpr)
- h->take_exception(HWACHA_CAUSE_TVEC_ILLEGAL_REGID, uint32_t(insn.bits()));
- h->get_ut_state(idx)->FPR.write(dst, value);
-}
-
-#define UT_READ_FPR(idx, src) read_fpr(h, insn, idx, src)
-#define UT_WRITE_FPR(idx, dst, value) write_fpr(h, insn, idx, dst, value)
-#define UT_FRS1(idx) (UT_READ_FPR(idx, INSN_RS1))
-#define UT_FRS2(idx) (UT_READ_FPR(idx, INSN_RS2))
-#define UT_FRS3(idx) (UT_READ_FPR(idx, INSN_RS3))
-#define UT_WRITE_FRD(idx, value) (UT_WRITE_FPR(idx, INSN_RD, value))
-
-#define VEC_SEG_LOAD(dst, func, inc) \
- VEC_SEG_ST_LOAD(dst, func, INSN_SEG*inc, inc)
-
-#define VEC_SEG_ST_LOAD(dst, func, stride, inc) \
- reg_t seg_addr = XS1; \
- for (uint32_t i=0; i<VL; i++) { \
- reg_t addr = seg_addr; \
- seg_addr += stride; \
- for (uint32_t j=0; j<INSN_SEG; j++) { \
- UT_WRITE_##dst(i, INSN_RD+j, p->get_mmu()->func(addr)); \
- addr += inc; \
- } \
- }
-
-#define VEC_SEG_STORE(src, func, inc) \
- VEC_SEG_ST_STORE(src, func, INSN_SEG*inc, inc)
-
-#define VEC_SEG_ST_STORE(src, func, stride, inc) \
- reg_t seg_addr = XS1; \
- for (uint32_t i=0; i<VL; i++) { \
- reg_t addr = seg_addr; \
- seg_addr += stride; \
- for (uint32_t j=0; j<INSN_SEG; j++) { \
- p->get_mmu()->func(addr, UT_READ_##src(i, INSN_RD+j)); \
- addr += inc; \
- } \
- }
-
-#define require_supervisor_hwacha \
- if (get_field(p->get_state()->mstatus, MSTATUS_PRV) < PRV_S) \
- h->take_exception(HWACHA_CAUSE_PRIVILEGED_INSTRUCTION, uint32_t(insn.bits()));
-
-#endif
+++ /dev/null
-#ifndef _DECODE_HWACHA_UT_H
-#define _DECODE_HWACHA_UT_H
-
-#include "decode.h"
-#include "decode_hwacha.h"
-#include "hwacha.h"
-#include "hwacha_xcpt.h"
-
-#undef RS1
-#undef RS2
-#undef WRITE_RD
-
-static inline reg_t read_rs1(hwacha_t* h, insn_t insn, uint32_t idx)
-{
- if (INSN_RS1 >= h->get_ct_state()->nxpr)
- h->take_exception(HWACHA_CAUSE_VF_ILLEGAL_REGID, VF_PC);
- return UT_RS1(idx);
-}
-
-static inline reg_t read_rs2(hwacha_t* h, insn_t insn, uint32_t idx)
-{
- if (INSN_RS2 >= h->get_ct_state()->nxpr)
- h->take_exception(HWACHA_CAUSE_VF_ILLEGAL_REGID, VF_PC);
- return UT_RS2(idx);
-}
-
-static inline void write_rd(hwacha_t* h, insn_t insn, uint32_t idx, reg_t value)
-{
- if (INSN_RD >= h->get_ct_state()->nxpr)
- h->take_exception(HWACHA_CAUSE_VF_ILLEGAL_REGID, VF_PC);
- UT_WRITE_RD(idx, value);
-}
-
-#define RS1 read_rs1(h, insn, UTIDX)
-#define RS2 read_rs2(h, insn, UTIDX)
-#define WRITE_RD(value) write_rd(h, insn, UTIDX, value)
-
-#undef FRS1
-#undef FRS2
-#undef FRS3
-#undef WRITE_FRD
-
-static inline reg_t read_frs1(hwacha_t* h, insn_t insn, uint32_t idx)
-{
- if (INSN_RS1 >= h->get_ct_state()->nfpr)
- h->take_exception(HWACHA_CAUSE_VF_ILLEGAL_REGID, VF_PC);
- return UT_FRS1(idx);
-}
-
-static inline reg_t read_frs2(hwacha_t* h, insn_t insn, uint32_t idx)
-{
- if (INSN_RS2 >= h->get_ct_state()->nfpr)
- h->take_exception(HWACHA_CAUSE_VF_ILLEGAL_REGID, VF_PC);
- return UT_FRS2(idx);
-}
-
-static inline reg_t read_frs3(hwacha_t* h, insn_t insn, uint32_t idx)
-{
- if (INSN_RS3 >= h->get_ct_state()->nfpr)
- h->take_exception(HWACHA_CAUSE_VF_ILLEGAL_REGID, VF_PC);
- return UT_FRS3(idx);
-}
-
-static inline void write_frd(hwacha_t* h, insn_t insn, uint32_t idx, reg_t value)
-{
- if (INSN_RD >= h->get_ct_state()->nfpr)
- h->take_exception(HWACHA_CAUSE_VF_ILLEGAL_REGID, VF_PC);
- UT_WRITE_FRD(idx, value);
-}
-
-#define FRS1 read_frs1(h, insn, UTIDX)
-#define FRS2 read_frs2(h, insn, UTIDX)
-#define FRS3 read_frs3(h, insn, UTIDX)
-#define WRITE_FRD(value) write_frd(h, insn, UTIDX, value)
-
-// we assume the vector unit has floating-point alus
-#undef require_fp
-#define require_fp
-
-#include "cvt16.h"
-
-#define HFRS1 cvt_hs(FRS1)
-#define HFRS2 cvt_hs(FRS2)
-#define HFRS3 cvt_hs(FRS3)
-
-#define WRITE_HFRD(value) write_frd(h, insn, UTIDX, cvt_sh(value, RM))
-
-#define sext16(x) ((sreg_t)(int16_t)(x))
-
-#endif
+++ /dev/null
-#ifndef ENCODINGS_HWACHA
-#define ENCODINGS_HWACHA
-
-#define MATCH_FCVT_H_LU 0x6c000053
-#define MASK_FCVT_H_LU 0xfff0007f
-#define MATCH_FMIN_H 0xc4000053
-#define MASK_FMIN_H 0xfe00707f
-#define MATCH_FCVT_WU_H 0x5c000053
-#define MASK_FCVT_WU_H 0xfff0007f
-#define MATCH_FDIV_H 0x1c000053
-#define MASK_FDIV_H 0xfe00007f
-#define MATCH_FCVT_H_WU 0x7c000053
-#define MASK_FCVT_H_WU 0xfff0007f
-#define MATCH_FSGNJ_H 0x2c000053
-#define MASK_FSGNJ_H 0xfe00707f
-#define MATCH_FNMSUB_H 0x400004b
-#define MASK_FNMSUB_H 0x600007f
-#define MATCH_FLE_H 0xbc000053
-#define MASK_FLE_H 0xfe00707f
-#define MATCH_FCVT_L_H 0x44000053
-#define MASK_FCVT_L_H 0xfff0007f
-#define MATCH_FNMADD_H 0x400004f
-#define MASK_FNMADD_H 0x600007f
-#define MATCH_FCVT_H_S 0x90000053
-#define MASK_FCVT_H_S 0xfff0007f
-#define MATCH_FCVT_H_W 0x74000053
-#define MASK_FCVT_H_W 0xfff0007f
-#define MATCH_FCVT_D_H 0x8c000053
-#define MASK_FCVT_D_H 0xfff0007f
-#define MATCH_FMAX_H 0xcc000053
-#define MASK_FMAX_H 0xfe00707f
-#define MATCH_FCVT_LU_H 0x4c000053
-#define MASK_FCVT_LU_H 0xfff0007f
-#define MATCH_FCVT_H_L 0x64000053
-#define MASK_FCVT_H_L 0xfff0007f
-#define MATCH_FMV_X_H 0xe4000053
-#define MASK_FMV_X_H 0xfff0707f
-#define MATCH_FCVT_H_D 0x92000053
-#define MASK_FCVT_H_D 0xfff0007f
-#define MATCH_FLT_H 0xb4000053
-#define MASK_FLT_H 0xfe00707f
-#define MATCH_FADD_H 0x4000053
-#define MASK_FADD_H 0xfe00007f
-#define MATCH_FCVT_S_H 0x84000053
-#define MASK_FCVT_S_H 0xfff0007f
-#define MATCH_FCVT_W_H 0x54000053
-#define MASK_FCVT_W_H 0xfff0007f
-#define MATCH_FMUL_H 0x14000053
-#define MASK_FMUL_H 0xfe00007f
-#define MATCH_FMADD_H 0x4000043
-#define MASK_FMADD_H 0x600007f
-#define MATCH_FSQRT_H 0x24000053
-#define MASK_FSQRT_H 0xfff0007f
-#define MATCH_FSGNJN_H 0x34000053
-#define MASK_FSGNJN_H 0xfe00707f
-#define MATCH_FSUB_H 0xc000053
-#define MASK_FSUB_H 0xfe00007f
-#define MATCH_FSH 0x1027
-#define MASK_FSH 0x707f
-#define MATCH_FSGNJX_H 0x3c000053
-#define MASK_FSGNJX_H 0xfe00707f
-#define MATCH_FLH 0x1007
-#define MASK_FLH 0x707f
-#define MATCH_FMSUB_H 0x4000047
-#define MASK_FMSUB_H 0x600007f
-#define MATCH_FEQ_H 0xac000053
-#define MASK_FEQ_H 0xfe00707f
-#define MATCH_FMV_H_X 0xf4000053
-#define MASK_FMV_H_X 0xfff0707f
-
-#define MASK_VF 0x1f0707f
-#define MASK_VFLSEGD 0x1ff0707f
-#define MASK_VFLSEGSTD 0x1e00707f
-#define MASK_VFLSEGSTW 0x1e00707f
-#define MASK_VFLSEGW 0x1ff0707f
-#define MASK_VFMVV 0xfff0707f
-#define MASK_VFMSV_S 0xfff0707f
-#define MASK_VFMSV_D 0xfff0707f
-#define MASK_VFSSEGD 0x1ff0707f
-#define MASK_VFSSEGSTD 0x1e00707f
-#define MASK_VFSSEGSTW 0x1e00707f
-#define MASK_VFSSEGW 0x1ff0707f
-#define MASK_VGETCFG 0xfffff07f
-#define MASK_VGETVL 0xfffff07f
-#define MASK_VLSEGB 0x1ff0707f
-#define MASK_VLSEGBU 0x1ff0707f
-#define MASK_VLSEGD 0x1ff0707f
-#define MASK_VLSEGH 0x1ff0707f
-#define MASK_VLSEGHU 0x1ff0707f
-#define MASK_VLSEGSTB 0x1e00707f
-#define MASK_VLSEGSTBU 0x1e00707f
-#define MASK_VLSEGSTD 0x1e00707f
-#define MASK_VLSEGSTH 0x1e00707f
-#define MASK_VLSEGSTHU 0x1e00707f
-#define MASK_VLSEGSTW 0x1e00707f
-#define MASK_VLSEGSTWU 0x1e00707f
-#define MASK_VLSEGW 0x1ff0707f
-#define MASK_VLSEGWU 0x1ff0707f
-#define MASK_VMSV 0xfff0707f
-#define MASK_VMVV 0xfff0707f
-#define MASK_VSETCFG 0x7fff
-#define MASK_VSETVL 0xfff0707f
-#define MASK_VSSEGB 0x1ff0707f
-#define MASK_VSSEGD 0x1ff0707f
-#define MASK_VSSEGH 0x1ff0707f
-#define MASK_VSSEGSTB 0x1e00707f
-#define MASK_VSSEGSTD 0x1e00707f
-#define MASK_VSSEGSTH 0x1e00707f
-#define MASK_VSSEGSTW 0x1e00707f
-#define MASK_VSSEGW 0x1ff0707f
-#define MASK_VXCPTAUX 0xfffff07f
-#define MASK_VXCPTCAUSE 0xfffff07f
-#define MASK_VXCPTEVAC 0xfff07fff
-#define MASK_VXCPTHOLD 0xfff07fff
-#define MASK_VXCPTKILL 0xffffffff
-#define MASK_VXCPTRESTORE 0xfff07fff
-#define MASK_VXCPTSAVE 0xfff07fff
-
-#define MATCH_VF 0x10202b
-#define MATCH_VFLSEGD 0x1600205b
-#define MATCH_VFLSEGSTD 0x1600305b
-#define MATCH_VFLSEGSTW 0x1400305b
-#define MATCH_VFLSEGW 0x1400205b
-#define MATCH_VFMVV 0x1000002b
-#define MATCH_VFMSV_S 0x1000202b
-#define MATCH_VFMSV_D 0x1200202b
-#define MATCH_VFSSEGD 0x1600207b
-#define MATCH_VFSSEGSTD 0x1600307b
-#define MATCH_VFSSEGSTW 0x1400307b
-#define MATCH_VFSSEGW 0x1400207b
-#define MATCH_VGETCFG 0x400b
-#define MATCH_VGETVL 0x200400b
-#define MATCH_VLSEGB 0x205b
-#define MATCH_VLSEGBU 0x800205b
-#define MATCH_VLSEGD 0x600205b
-#define MATCH_VLSEGH 0x200205b
-#define MATCH_VLSEGHU 0xa00205b
-#define MATCH_VLSEGSTB 0x305b
-#define MATCH_VLSEGSTBU 0x800305b
-#define MATCH_VLSEGSTD 0x600305b
-#define MATCH_VLSEGSTH 0x200305b
-#define MATCH_VLSEGSTHU 0xa00305b
-#define MATCH_VLSEGSTW 0x400305b
-#define MATCH_VLSEGSTWU 0xc00305b
-#define MATCH_VLSEGW 0x400205b
-#define MATCH_VLSEGWU 0xc00205b
-#define MATCH_VMSV 0x200202b
-#define MATCH_VMVV 0x200002b
-#define MATCH_VSETCFG 0x200b
-#define MATCH_VSETVL 0x600b
-#define MATCH_VSSEGB 0x207b
-#define MATCH_VSSEGD 0x600207b
-#define MATCH_VSSEGH 0x200207b
-#define MATCH_VSSEGSTB 0x307b
-#define MATCH_VSSEGSTD 0x600307b
-#define MATCH_VSSEGSTH 0x200307b
-#define MATCH_VSSEGSTW 0x400307b
-#define MATCH_VSSEGW 0x400207b
-#define MATCH_VXCPTAUX 0x200402b
-#define MATCH_VXCPTCAUSE 0x402b
-#define MATCH_VXCPTEVAC 0x600302b
-#define MATCH_VXCPTHOLD 0x800302b
-#define MATCH_VXCPTKILL 0x400302b
-#define MATCH_VXCPTRESTORE 0x200302b
-#define MATCH_VXCPTSAVE 0x302b
-
-#endif /* ENCODINGS_HWACHA */
+++ /dev/null
-#include "hwacha.h"
-#include "hwacha_xcpt.h"
-#include "mmu.h"
-#include "trap.h"
-#include <stdexcept>
-
-REGISTER_EXTENSION(hwacha, []() { return new hwacha_t; })
-
-void ct_state_t::reset()
-{
- nxpr = 32;
- nfpr = 32;
- maxvl = 32;
- vl = 0;
- count = 0;
- prec = 64;
-
- vf_pc = -1;
-}
-
-void ut_state_t::reset()
-{
- memset(this, 0, sizeof(*this));
-}
-
-void hwacha_t::reset()
-{
- ct_state.reset();
- for (int i=0; i<max_uts; i++)
- ut_state[i].reset();
-}
-
-static reg_t custom(processor_t* p, insn_t insn, reg_t pc)
-{
- require_accelerator;
- hwacha_t* h = static_cast<hwacha_t*>(p->get_extension());
- bool matched = false;
- reg_t npc = -1;
-
- try
- {
- #define DECLARE_INSN(name, match, mask) \
- extern reg_t hwacha_##name(processor_t*, insn_t, reg_t); \
- if ((insn.bits() & mask) == match) { \
- npc = hwacha_##name(p, insn, pc); \
- matched = true; \
- }
- #include "opcodes_hwacha.h"
- #undef DECLARE_INSN
- }
- catch (trap_instruction_access_fault& t)
- {
- h->take_exception(HWACHA_CAUSE_VF_FAULT_FETCH, h->get_ct_state()->vf_pc);
- }
- catch (trap_illegal_instruction& t)
- {
- h->take_exception(HWACHA_CAUSE_VF_ILLEGAL_INSTRUCTION, h->get_ct_state()->vf_pc);
- }
- catch (trap_load_address_misaligned& t)
- {
- h->take_exception(HWACHA_CAUSE_MISALIGNED_LOAD, t.get_badvaddr());
- }
- catch (trap_store_address_misaligned& t)
- {
- h->take_exception(HWACHA_CAUSE_MISALIGNED_STORE, t.get_badvaddr());
- }
- catch (trap_load_access_fault& t)
- {
- h->take_exception(HWACHA_CAUSE_FAULT_LOAD, t.get_badvaddr());
- }
- catch (trap_store_access_fault& t)
- {
- h->take_exception(HWACHA_CAUSE_FAULT_STORE, t.get_badvaddr());
- }
-
- if (!matched)
- h->take_exception(HWACHA_CAUSE_ILLEGAL_INSTRUCTION, uint32_t(insn.bits()));
-
- return npc;
-}
-
-std::vector<insn_desc_t> hwacha_t::get_instructions()
-{
- std::vector<insn_desc_t> insns;
- insns.push_back((insn_desc_t){0x0b, 0x7f, &::illegal_instruction, custom});
- insns.push_back((insn_desc_t){0x2b, 0x7f, &::illegal_instruction, custom});
- insns.push_back((insn_desc_t){0x5b, 0x7f, &::illegal_instruction, custom});
- insns.push_back((insn_desc_t){0x7b, 0x7f, &::illegal_instruction, custom});
- return insns;
-}
-
-bool hwacha_t::vf_active()
-{
- for (uint32_t i=0; i<get_ct_state()->vl; i++) {
- if (get_ut_state(i)->run)
- return true;
- }
- return false;
-}
-
-void hwacha_t::take_exception(reg_t c, reg_t a)
-{
- cause = c;
- aux = a;
- raise_interrupt();
- throw std::logic_error("unreachable!");
-}
+++ /dev/null
-#ifndef _HWACHA_H
-#define _HWACHA_H
-
-#include "extension.h"
-
-struct ct_state_t
-{
- void reset();
-
- uint32_t nxpr;
- uint32_t nfpr;
- uint32_t maxvl;
- uint32_t vl;
- uint32_t count;
- uint32_t prec;
-
- reg_t vf_pc;
-};
-
-struct ut_state_t
-{
- void reset();
-
- bool run;
- regfile_t<reg_t, 32, true> XPR;
- regfile_t<reg_t, 32, false> FPR;
-};
-
-class hwacha_t : public extension_t
-{
-public:
- hwacha_t() : cause(0), aux(0), debug(false) {}
- std::vector<insn_desc_t> get_instructions();
- std::vector<disasm_insn_t*> get_disasms();
- const char* name() { return "hwacha"; }
- void reset();
- void set_debug(bool value) { debug = value; }
-
- ct_state_t* get_ct_state() { return &ct_state; }
- ut_state_t* get_ut_state(int idx) { return &ut_state[idx]; }
- bool vf_active();
- reg_t get_cause() { return cause; }
- reg_t get_aux() { return aux; }
- void take_exception(reg_t, reg_t);
- void clear_exception() { clear_interrupt(); }
-
- bool get_debug() { return debug; }
- disassembler_t* get_ut_disassembler() { return &ut_disassembler; }
-
- static const int max_uts = 2048;
-
-private:
- ct_state_t ct_state;
- ut_state_t ut_state[max_uts];
- reg_t cause;
- reg_t aux;
-
- disassembler_t ut_disassembler;
- bool debug;
-};
-
-#endif
+++ /dev/null
-hwacha_subproject_deps = \
- spike_main \
- riscv \
- softfloat \
-
-hwacha_install_prog_srcs = \
-
-hwacha_hdrs = \
- hwacha.h \
- hwacha_xcpt.h \
- decode_hwacha.h \
- decode_hwacha_ut.h \
- opcodes_hwacha.h \
- opcodes_hwacha_ut.h \
- insn_template_hwacha.h \
- insn_template_hwacha_ut.h \
-
-hwacha_precompiled_hdrs = \
- insn_template_hwacha.h \
- insn_template_hwacha_ut.h \
-
-hwacha_srcs = \
- hwacha.cc \
- hwacha_disasm.cc \
- cvt16.cc \
- $(hwacha_gen_srcs) \
- $(hwacha_ut_gen_srcs) \
-
-hwacha_test_srcs =
-
-hwacha_gen_srcs = \
- $(addsuffix .cc, $(call get_insn_list,$(src_dir)/hwacha/opcodes_hwacha.h))
-
-$(hwacha_gen_srcs): %.cc: insns/%.h insn_template_hwacha.cc
- sed 's/NAME/$(subst .cc,,$@)/' $(src_dir)/hwacha/insn_template_hwacha.cc | sed 's/OPCODE/$(call get_opcode,$(src_dir)/hwacha/opcodes_hwacha.h,$(subst .cc,,$@))/' > $@
-
-hwacha_ut_gen_srcs = \
- $(addsuffix .cc, $(call get_insn_list,$(src_dir)/hwacha/opcodes_hwacha_ut.h))
-
-$(hwacha_ut_gen_srcs): %.cc: insns_ut/%.h insn_template_hwacha_ut.cc
- sed 's/NAME/$(subst .cc,,$@)/' $(src_dir)/hwacha/insn_template_hwacha_ut.cc | sed 's/OPCODE/$(call get_opcode,$(src_dir)/hwacha/opcodes_hwacha_ut.h,$(subst .cc,,$@))/' > $@
-
-hwacha_junk = \
- $(hwacha_gen_srcs) \
- $(hwacha_ut_gen_srcs) \
+++ /dev/null
-#include "hwacha.h"
-
-static const char* xpr[] = {
- "zero", "ra", "s0", "s1", "s2", "s3", "s4", "s5",
- "s6", "s7", "s8", "s9", "s10", "s11", "sp", "tp",
- "v0", "v1", "a0", "a1", "a2", "a3", "a4", "a5",
- "a6", "a7", "t0", "t1", "t2", "t3", "t4", "gp"
-};
-
-static const char* fpr[] = {
- "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
- "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15",
- "fv0", "fv1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
- "fa6", "fa7", "ft0", "ft1", "ft2", "ft3", "ft4", "ft5"
-};
-
-static const char* vxpr[] = {
- "vx0", "vx1", "vx2", "vx3", "vx4", "vx5", "vx6", "vx7",
- "vx8", "vx9", "vx10", "vx11", "vx12", "vx13", "vx14", "vx15",
- "vx16", "vx17", "vx18", "vx19", "vx20", "vx21", "vx22", "vx23",
- "vx24", "vx25", "vx26", "vx27", "vx28", "vx29", "vx30", "vx31"
-};
-
-static const char* vfpr[] = {
- "vf0", "vf1", "vf2", "vf3", "vf4", "vf5", "vf6", "vf7",
- "vf8", "vf9", "vf10", "vf11", "vf12", "vf13", "vf14", "vf15",
- "vf16", "vf17", "vf18", "vf19", "vf20", "vf21", "vf22", "vf23",
- "vf24", "vf25", "vf26", "vf27", "vf28", "vf29", "vf30", "vf31"
-};
-
-struct : public arg_t {
- std::string to_string(insn_t insn) const {
- return xpr[insn.rs1()];
- }
-} xrs1;
-
-struct : public arg_t {
- std::string to_string(insn_t insn) const {
- return xpr[insn.rs2()];
- }
-} xrs2;
-
-struct : public arg_t {
- std::string to_string(insn_t insn) const {
- return xpr[insn.rd()];
- }
-} xrd;
-
-struct : public arg_t {
- std::string to_string(insn_t insn) const {
- return fpr[insn.rd()];
- }
-} frd;
-
-struct : public arg_t {
- std::string to_string(insn_t insn) const {
- return fpr[insn.rs1()];
- }
-} frs1;
-
-struct : public arg_t {
- std::string to_string(insn_t insn) const {
- return fpr[insn.rs2()];
- }
-} frs2;
-
-struct : public arg_t {
- std::string to_string(insn_t insn) const {
- return fpr[insn.rs3()];
- }
-} frs3;
-
-struct : public arg_t {
- std::string to_string(insn_t insn) const {
- return vxpr[insn.rd()];
- }
-} vxrd;
-
-struct : public arg_t {
- std::string to_string(insn_t insn) const {
- return vxpr[insn.rs1()];
- }
-} vxrs1;
-
-struct : public arg_t {
- std::string to_string(insn_t insn) const {
- return vfpr[insn.rd()];
- }
-} vfrd;
-
-struct : public arg_t {
- std::string to_string(insn_t insn) const {
- return vfpr[insn.rs1()];
- }
-} vfrs1;
-
-struct : public arg_t {
- std::string to_string(insn_t insn) const {
- return std::to_string(insn.i_imm() & 0x3f);
- }
-} nxregs;
-
-struct : public arg_t {
- std::string to_string(insn_t insn) const {
- return std::to_string((insn.i_imm() >> 6) & 0x3f);
- }
-} nfregs;
-
-struct : public arg_t {
- std::string to_string(insn_t insn) const {
- return std::to_string((int)insn.s_imm()) + '(' + xpr[insn.rs1()] + ')';
- }
-} vf_addr;
-
-std::vector<disasm_insn_t*> hwacha_t::get_disasms()
-{
- std::vector<disasm_insn_t*> insns;
-
- #define DECLARE_INSN(code, match, mask) \
- const uint32_t match_##code = match; \
- const uint32_t mask_##code = mask;
- #include "opcodes_hwacha.h"
- #undef DECLARE_INSN
-
- #define DISASM_INSN(name, code, extra, ...) \
- insns.push_back(new disasm_insn_t(name, match_##code, mask_##code | (extra), __VA_ARGS__));
-
- DISASM_INSN("vsetcfg", vsetcfg, 0, {&xrs1, &nxregs, &nfregs});
- DISASM_INSN("vsetvl", vsetvl, 0, {&xrd, &xrs1});
- DISASM_INSN("vgetcfg", vgetcfg, 0, {&xrd});
- DISASM_INSN("vgetvl", vgetvl, 0, {&xrd});
-
- DISASM_INSN("vmvv", vmvv, 0, {&vxrd, &vxrs1});
- DISASM_INSN("vmsv", vmsv, 0, {&vxrd, &xrs1});
- DISASM_INSN("vfmvv", vfmvv, 0, {&vfrd, &vfrs1});
- DISASM_INSN("vfmsv.s", vfmsv_s, 0, {&vfrd, &xrs1});
- DISASM_INSN("vfmsv.d", vfmsv_d, 0, {&vfrd, &xrs1});
- DISASM_INSN("vf", vf, 0, {&vf_addr});
-
- DISASM_INSN("vxcptcause", vxcptcause, 0, {&xrd});
- DISASM_INSN("vxcptaux", vxcptaux, 0, {&xrd});
- DISASM_INSN("vxcptevac", vxcptevac, 0, {&xrs1});
- DISASM_INSN("vxcpthold", vxcpthold, 0, {&xrs1});
- DISASM_INSN("vxcptkill", vxcptkill, 0, {});
-
- const uint32_t mask_vseglen = 0x7UL << 29;
-
- #define DISASM_VMEM_INSN(name1, name2, code, ...) \
- DISASM_INSN(name1, code, mask_vseglen, __VA_ARGS__) \
- DISASM_INSN(name2, code, 0, __VA_ARGS__) \
-
- DISASM_VMEM_INSN("vld", "vlsegd", vlsegd, {&vxrd, &xrs1});
- DISASM_VMEM_INSN("vlw", "vlsegw", vlsegw, {&vxrd, &xrs1});
- DISASM_VMEM_INSN("vlwu", "vlsegwu", vlsegwu, {&vxrd, &xrs1});
- DISASM_VMEM_INSN("vlh", "vlsegh", vlsegh, {&vxrd, &xrs1});
- DISASM_VMEM_INSN("vlhu", "vlseghu", vlseghu, {&vxrd, &xrs1});
- DISASM_VMEM_INSN("vlb", "vlsegb", vlsegb, {&vxrd, &xrs1});
- DISASM_VMEM_INSN("vlbu", "vlsegbu", vlsegbu, {&vxrd, &xrs1});
- DISASM_VMEM_INSN("vfld", "vflsegd", vflsegd, {&vfrd, &xrs1});
- DISASM_VMEM_INSN("vflw", "vflsegw", vflsegw, {&vfrd, &xrs1});
-
- DISASM_VMEM_INSN("vlstd", "vlsegstd", vlsegstd, {&vxrd, &xrs1, &xrs2});
- DISASM_VMEM_INSN("vlstw", "vlsegstw", vlsegstw, {&vxrd, &xrs1, &xrs2});
- DISASM_VMEM_INSN("vlstwu", "vlsegstwu", vlsegstwu, {&vxrd, &xrs1, &xrs2});
- DISASM_VMEM_INSN("vlsth", "vlsegsth", vlsegsth, {&vxrd, &xrs1, &xrs2});
- DISASM_VMEM_INSN("vlsthu", "vlsegsthu", vlsegsthu, {&vxrd, &xrs1, &xrs2});
- DISASM_VMEM_INSN("vlstb", "vlsegstb", vlsegstb, {&vxrd, &xrs1, &xrs2});
- DISASM_VMEM_INSN("vlstbu", "vlsegstbu", vlsegstbu, {&vxrd, &xrs1, &xrs2});
- DISASM_VMEM_INSN("vflstd", "vflsegstd", vflsegstd, {&vfrd, &xrs1, &xrs2});
- DISASM_VMEM_INSN("vflstw", "vflsegstw", vflsegstw, {&vfrd, &xrs1, &xrs2});
-
- DISASM_VMEM_INSN("vsd", "vssegd", vssegd, {&vxrd, &xrs1});
- DISASM_VMEM_INSN("vsw", "vssegw", vssegw, {&vxrd, &xrs1});
- DISASM_VMEM_INSN("vsh", "vssegh", vssegh, {&vxrd, &xrs1});
- DISASM_VMEM_INSN("vsb", "vssegb", vssegb, {&vxrd, &xrs1});
- DISASM_VMEM_INSN("vfsd", "vfssegd", vfssegd, {&vfrd, &xrs1});
- DISASM_VMEM_INSN("vfsw", "vfssegw", vfssegw, {&vfrd, &xrs1});
-
- DISASM_VMEM_INSN("vsstd", "vssegstd", vssegstd, {&vxrd, &xrs1, &xrs2});
- DISASM_VMEM_INSN("vsstw", "vssegstw", vssegstw, {&vxrd, &xrs1, &xrs2});
- DISASM_VMEM_INSN("vssth", "vssegsth", vssegsth, {&vxrd, &xrs1, &xrs2});
- DISASM_VMEM_INSN("vsstb", "vssegstb", vssegstb, {&vxrd, &xrs1, &xrs2});
- DISASM_VMEM_INSN("vfsstd", "vfssegstd", vfssegstd, {&vfrd, &xrs1, &xrs2});
- DISASM_VMEM_INSN("vfsstw", "vfssegstw", vfssegstw, {&vfrd, &xrs1, &xrs2});
-
- #define DECLARE_INSN(code, match, mask) \
- const uint32_t match_##code = match; \
- const uint32_t mask_##code = mask;
- #include "opcodes_hwacha_ut.h"
- #undef DECLARE_INSN
-
- #define DISASM_UT_INSN(name, code, extra, ...) \
- ut_disassembler.add_insn(new disasm_insn_t(name, match_##code, mask_##code | (extra), __VA_ARGS__));
-
- DISASM_UT_INSN("stop", ut_stop, 0, {});
- DISASM_UT_INSN("utidx", ut_utidx, 0, {&xrd});
- DISASM_UT_INSN("movz", ut_movz, 0, {&xrd, &xrs1, &xrs2});
- DISASM_UT_INSN("movn", ut_movn, 0, {&xrd, &xrs1, &xrs2});
- DISASM_UT_INSN("fmovz", ut_fmovz, 0, {&frd, &xrs1, &frs2});
- DISASM_UT_INSN("fmovn", ut_fmovn, 0, {&frd, &xrs1, &frs2});
-
- return insns;
-}
+++ /dev/null
-#ifndef _HWACHA_XCPT_H
-#define _HWACHA_XCPT_H
-
-#include "encoding.h"
-
-#define HWACHA_CAUSE_ILLEGAL_CFG CAUSE_ILLEGAL_INSTRUCTION // AUX: 0=illegal nxpr, 1=illegal nfpr
-#define HWACHA_CAUSE_ILLEGAL_INSTRUCTION CAUSE_ILLEGAL_INSTRUCTION // AUX: instruction
-#define HWACHA_CAUSE_PRIVILEGED_INSTRUCTION CAUSE_ILLEGAL_INSTRUCTION // AUX: instruction
-#define HWACHA_CAUSE_TVEC_ILLEGAL_REGID CAUSE_ILLEGAL_INSTRUCTION // AUX: instruction
-#define HWACHA_CAUSE_VF_MISALIGNED_FETCH CAUSE_MISALIGNED_FETCH // AUX: pc
-#define HWACHA_CAUSE_VF_FAULT_FETCH CAUSE_FAULT_FETCH // AUX: pc
-#define HWACHA_CAUSE_VF_ILLEGAL_INSTRUCTION CAUSE_ILLEGAL_INSTRUCTION // AUX: pc
-#define HWACHA_CAUSE_VF_ILLEGAL_REGID CAUSE_ILLEGAL_INSTRUCTION // AUX: pc
-#define HWACHA_CAUSE_MISALIGNED_LOAD CAUSE_MISALIGNED_LOAD // AUX: badvaddr
-#define HWACHA_CAUSE_MISALIGNED_STORE CAUSE_MISALIGNED_STORE // AUX: badvaddr
-#define HWACHA_CAUSE_FAULT_LOAD CAUSE_FAULT_LOAD // AUX: badvaddr
-#define HWACHA_CAUSE_FAULT_STORE CAUSE_FAULT_STORE // AUX: badvaddr
-
-#endif
+++ /dev/null
-// See LICENSE for license details.
-#include "insn_template_hwacha.h"
-
-reg_t hwacha_NAME(processor_t* p, insn_t insn, reg_t pc)
-{
- int xlen = 64;
- reg_t npc = sext_xlen(pc + insn_length(OPCODE));
- hwacha_t* h = static_cast<hwacha_t*>(p->get_extension());
- rocc_insn_union_t u;
- u.i = insn;
- reg_t xs1 = u.r.xs1 ? RS1 : -1;
- reg_t xs2 = u.r.xs2 ? RS2 : -1;
- reg_t xd = -1;
- #include "insns/NAME.h"
- if (u.r.xd) WRITE_RD(xd);
- return npc;
-}
+++ /dev/null
-#include "hwacha.h"
-#include "decode_hwacha.h"
-#include "encodings_hwacha.h"
-#include "rocc.h"
-#include <assert.h>
+++ /dev/null
-// See LICENSE for license details.
-#include "insn_template_hwacha_ut.h"
-
-reg_t hwacha_NAME(processor_t* p, insn_t insn, reg_t pc)
-{
- int xlen = 64;
- reg_t npc = sext_xlen(pc + insn_length(OPCODE));
- hwacha_t* h = static_cast<hwacha_t*>(p->get_extension());
- do {
- #include "insns_ut/NAME.h"
- WRITE_UTIDX(UTIDX+1);
- } while (UTIDX < VL);
- WRITE_UTIDX(0);
- return npc;
-}
+++ /dev/null
-#include "hwacha.h"
-#include "mulhi.h"
-#include "decode_hwacha_ut.h"
-#include "softfloat.h"
-#include "platform.h" // softfloat isNaNF32UI, etc.
-#include "internals.h" // ditto
-#include <assert.h>
+++ /dev/null
-if (VL) {
- if (!h->vf_active()) {
- WRITE_VF_PC(XS1 + insn.s_imm());
- for (uint32_t i=0; i<VL; i++)
- h->get_ut_state(i)->run = true;
- }
-
-vf_loop:
-
- if (VF_PC & 3)
- h->take_exception(HWACHA_CAUSE_VF_MISALIGNED_FETCH, VF_PC);
-
- insn_t ut_insn = p->get_mmu()->load_insn(VF_PC).insn;
-
- bool matched = false;
-
- #define DECLARE_INSN(name, match, mask) \
- extern reg_t hwacha_##name(processor_t*, insn_t, reg_t); \
- if ((ut_insn.bits() & mask) == match) { \
- WRITE_VF_PC(hwacha_##name(p, ut_insn, VF_PC)); \
- matched = true; \
- }
- #include "opcodes_hwacha_ut.h"
- #undef DECLARE_INSN
-
- if (!matched)
- h->take_exception(HWACHA_CAUSE_VF_ILLEGAL_INSTRUCTION, VF_PC);
-
- if (!h->get_debug()) {
- if (h->vf_active())
- goto vf_loop;
- } else {
- fprintf(stderr, "vf block: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
- VF_PC, ut_insn.bits(), h->get_ut_disassembler()->disassemble(ut_insn).c_str());
- if (h->vf_active())
- npc = pc;
- }
-}
+++ /dev/null
-VEC_SEG_LOAD(FPR, load_int64, 8);
+++ /dev/null
-VEC_SEG_ST_LOAD(FPR, load_int64, XS2, 8);
+++ /dev/null
-VEC_SEG_ST_LOAD(FPR, load_int32, XS2, 4);
+++ /dev/null
-VEC_SEG_LOAD(FPR, load_int32, 4);
+++ /dev/null
-for (uint32_t i=0; i<VL; i++) {
- UT_WRITE_FRD(i, XS1);
-}
+++ /dev/null
-for (uint32_t i=0; i<VL; i++) {
- UT_WRITE_FRD(i, XS1);
-}
+++ /dev/null
-for (uint32_t i=0; i<VL; i++) {
- UT_WRITE_FRD(i, UT_FRS1(i));
-}
+++ /dev/null
-VEC_SEG_STORE(FPR, store_uint64, 8);
+++ /dev/null
-VEC_SEG_ST_STORE(FPR, store_uint64, XS2, 8);
+++ /dev/null
-VEC_SEG_ST_STORE(FPR, store_uint32, XS2, 4);
+++ /dev/null
-VEC_SEG_STORE(FPR, store_uint32, 4);
+++ /dev/null
-WRITE_XRD((NXPR & 0x3f) | ((NFPR & 0x3f) << 6));
+++ /dev/null
-WRITE_XRD(VL);
+++ /dev/null
-VEC_SEG_LOAD(XPR, load_int8, 1);
+++ /dev/null
-VEC_SEG_LOAD(XPR, load_uint8, 1);
+++ /dev/null
-VEC_SEG_LOAD(XPR, load_int64, 8);
+++ /dev/null
-VEC_SEG_LOAD(XPR, load_int16, 2);
+++ /dev/null
-VEC_SEG_LOAD(XPR, load_uint16, 2);
+++ /dev/null
-VEC_SEG_ST_LOAD(XPR, load_int8, XS2, 1);
+++ /dev/null
-VEC_SEG_ST_LOAD(XPR, load_uint8, XS2, 1);
+++ /dev/null
-VEC_SEG_ST_LOAD(XPR, load_int64, XS2, 8);
+++ /dev/null
-VEC_SEG_ST_LOAD(XPR, load_int16, XS2, 2);
+++ /dev/null
-VEC_SEG_ST_LOAD(XPR, load_uint16, XS2, 2);
+++ /dev/null
-VEC_SEG_ST_LOAD(XPR, load_int32, XS2, 4);
+++ /dev/null
-VEC_SEG_ST_LOAD(XPR, load_uint32, XS2, 4);
+++ /dev/null
-VEC_SEG_LOAD(XPR, load_int32, 4);
+++ /dev/null
-VEC_SEG_LOAD(XPR, load_uint32, 4);
+++ /dev/null
-for (uint32_t i=0; i<VL; i++)
- UT_WRITE_RD(i, XS1);
+++ /dev/null
-for (uint32_t i=0; i<VL; i++) {
- UT_WRITE_RD(i, UT_RS1(i));
-}
+++ /dev/null
-uint32_t nxpr = (XS1 & 0x3f) + (insn.i_imm() & 0x3f);
-uint32_t nfpr = ((XS1 >> 6) & 0x3f) + ((insn.i_imm() >> 6) & 0x3f);
-if (nxpr > 32)
- h->take_exception(HWACHA_CAUSE_ILLEGAL_CFG, 0);
-if (nfpr > 32)
- h->take_exception(HWACHA_CAUSE_ILLEGAL_CFG, 1);
-WRITE_NXPR(nxpr);
-WRITE_NFPR(nfpr);
-uint32_t maxvl;
-if (nxpr + nfpr < 2)
- maxvl = 8 * 256;
-else
- maxvl = 8 * (256 / (nxpr-1 + nfpr));
-WRITE_MAXVL(maxvl);
-WRITE_VL(0);
+++ /dev/null
-WRITE_RD(insn.u_imm());
+++ /dev/null
-uint32_t vl = std::min(MAXVL, (uint32_t)XS1);
-WRITE_VL(vl);
-WRITE_XRD(vl);
+++ /dev/null
-VEC_SEG_STORE(XPR, store_uint8, 1);
+++ /dev/null
-VEC_SEG_STORE(XPR, store_uint64, 8);
+++ /dev/null
-VEC_SEG_STORE(XPR, store_uint16, 2);
+++ /dev/null
-VEC_SEG_ST_STORE(XPR, store_uint8, XS2, 1);
+++ /dev/null
-VEC_SEG_ST_STORE(XPR, store_uint64, XS2, 8);
+++ /dev/null
-VEC_SEG_ST_STORE(XPR, store_uint16, XS2, 2);
+++ /dev/null
-VEC_SEG_ST_STORE(XPR, store_uint32, XS2, 4);
+++ /dev/null
-VEC_SEG_STORE(XPR, store_uint32, 4);
+++ /dev/null
-require_supervisor_hwacha;
-xd = h->get_aux();
+++ /dev/null
-require_supervisor_hwacha;
-h->clear_exception();
-xd = h->get_cause();
+++ /dev/null
-require_supervisor_hwacha;
-reg_t addr = XS1;
-
-#define STORE_B(addr, value) \
- p->get_mmu()->store_uint8(addr, value); \
- addr += 1; \
-
-#define STORE_W(addr, value) \
- p->get_mmu()->store_uint32(addr, value); \
- addr += 4; \
-
-#define STORE_D(addr, value) \
- p->get_mmu()->store_uint64(addr, value); \
- addr += 8; \
-
-// to be compliant with the evac structure
-STORE_D(addr, (uint64_t)-1);
-
-STORE_W(addr, NXPR);
-STORE_W(addr, NFPR);
-STORE_W(addr, MAXVL);
-STORE_W(addr, VL);
-STORE_W(addr, UTIDX);
-STORE_W(addr, PREC);
-
-STORE_D(addr, VF_PC);
-
-for (uint32_t x=1; x<NXPR; x++) {
- for (uint32_t i=0; i<VL; i++) {
- STORE_D(addr, UT_READ_XPR(i, x));
- }
-}
-
-for (uint32_t f=0; f<NFPR; f++) {
- for (uint32_t i=0; i<VL; i++) {
- STORE_D(addr, UT_READ_FPR(i, f));
- }
-}
-
-for (uint32_t i=0; i<VL; i++) {
- STORE_B(addr, h->get_ut_state(i)->run);
-}
-
-#undef STORE_B
-#undef STORE_W
-#undef STORE_D
-
-#include "insns/vxcptkill.h"
+++ /dev/null
-require_supervisor_hwacha;
-reg_t addr = XS1;
-
-#define LOAD_B(addr) \
- (addr += 1, p->get_mmu()->load_uint8(addr-1))
-
-#define LOAD_W(addr) \
- (addr += 4, p->get_mmu()->load_uint32(addr-4))
-
-#define LOAD_D(addr) \
- (addr += 8, p->get_mmu()->load_uint64(addr-8))
-
-// to be compliant with the evac structure
-addr += 8;
-
-WRITE_NXPR(LOAD_W(addr));
-WRITE_NFPR(LOAD_W(addr));
-WRITE_MAXVL(LOAD_W(addr));
-WRITE_VL(LOAD_W(addr));
-WRITE_UTIDX(LOAD_W(addr));
-WRITE_PREC(LOAD_W(addr));
-WRITE_VF_PC(LOAD_D(addr));
-
-for (uint32_t x=1; x<NXPR; x++) {
- for (uint32_t i=0; i<VL; i++) {
- UT_WRITE_XPR(i, x, LOAD_D(addr));
- }
-}
-
-for (uint32_t f=0; f<NFPR; f++) {
- for (uint32_t i=0; i<VL; i++) {
- UT_WRITE_FPR(i, f, LOAD_D(addr));
- }
-}
-
-for (uint32_t i=0; i<VL; i++) {
- h->get_ut_state(i)->run = LOAD_B(addr);
-}
-
-#undef LOAD_B
-#undef LOAD_W
-#undef LOAD_D
+++ /dev/null
-require_supervisor_hwacha;
-h->get_ct_state()->reset();
-for (uint32_t i=0; i<h->max_uts; i++)
- h->get_ut_state(i)->reset();
+++ /dev/null
-../../riscv/insns/add.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/addi.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/addiw.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/addw.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/amoadd_d.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/amoadd_w.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/amoand_d.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/amoand_w.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/amomax_d.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/amomax_w.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/amomaxu_d.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/amomaxu_w.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/amomin_d.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/amomin_w.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/amominu_d.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/amominu_w.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/amoor_d.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/amoor_w.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/amoswap_d.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/amoswap_w.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/amoxor_d.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/amoxor_w.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/and.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/andi.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/auipc.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/div.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/divu.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/divuw.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/divw.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fadd_d.h
\ No newline at end of file
+++ /dev/null
-require_fp;
-softfloat_roundingMode = RM;
-WRITE_HFRD(f32_mulAdd(HFRS1, 0x3f800000, HFRS2));
-set_fp_exceptions;
+++ /dev/null
-../../riscv/insns/fadd_s.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fclass_d.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fclass_s.h
\ No newline at end of file
+++ /dev/null
-require_fp;
-softfloat_roundingMode = RM;
-WRITE_FRD(f32_to_f64(HFRS1));
-set_fp_exceptions;
+++ /dev/null
-../../riscv/insns/fcvt_d_l.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fcvt_d_lu.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fcvt_d_s.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fcvt_d_w.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fcvt_d_wu.h
\ No newline at end of file
+++ /dev/null
-require_fp;
-softfloat_roundingMode = RM;
-WRITE_HFRD(f64_to_f32(FRS1));
-set_fp_exceptions;
+++ /dev/null
-require_rv64;
-require_fp;
-softfloat_roundingMode = RM;
-WRITE_HFRD(i64_to_f32(RS1));
-set_fp_exceptions;
+++ /dev/null
-require_rv64;
-require_fp;
-softfloat_roundingMode = RM;
-WRITE_HFRD(ui64_to_f32(RS1));
-set_fp_exceptions;
+++ /dev/null
-require_fp;
-WRITE_FRD(cvt_sh(FRS1, RM));
-set_fp_exceptions;
+++ /dev/null
-require_fp;
-softfloat_roundingMode = RM;
-WRITE_HFRD(i32_to_f32((int32_t)RS1));
-set_fp_exceptions;
+++ /dev/null
-require_fp;
-softfloat_roundingMode = RM;
-WRITE_HFRD(ui32_to_f32((uint32_t)RS1));
-set_fp_exceptions;
+++ /dev/null
-../../riscv/insns/fcvt_l_d.h
\ No newline at end of file
+++ /dev/null
-require_rv64;
-require_fp;
-softfloat_roundingMode = RM;
-WRITE_RD(f32_to_i64(HFRS1, RM, true));
-set_fp_exceptions;
+++ /dev/null
-../../riscv/insns/fcvt_l_s.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fcvt_lu_d.h
\ No newline at end of file
+++ /dev/null
-require_rv64;
-require_fp;
-softfloat_roundingMode = RM;
-WRITE_RD(f32_to_ui64(HFRS1, RM, true));
-set_fp_exceptions;
+++ /dev/null
-../../riscv/insns/fcvt_lu_s.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fcvt_s_d.h
\ No newline at end of file
+++ /dev/null
-require_fp;
-WRITE_FRD(HFRS1);
-set_fp_exceptions;
+++ /dev/null
-../../riscv/insns/fcvt_s_l.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fcvt_s_lu.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fcvt_s_w.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fcvt_s_wu.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fcvt_w_d.h
\ No newline at end of file
+++ /dev/null
-require_fp;
-softfloat_roundingMode = RM;
-WRITE_RD(sext32(f32_to_i32(HFRS1, RM, true)));
-set_fp_exceptions;
+++ /dev/null
-../../riscv/insns/fcvt_w_s.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fcvt_wu_d.h
\ No newline at end of file
+++ /dev/null
-require_fp;
-softfloat_roundingMode = RM;
-WRITE_RD(sext32(f32_to_ui32(HFRS1, RM, true)));
-set_fp_exceptions;
+++ /dev/null
-../../riscv/insns/fcvt_wu_s.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fdiv_d.h
\ No newline at end of file
+++ /dev/null
-require_fp;
-softfloat_roundingMode = RM;
-WRITE_HFRD(f32_div(HFRS1, HFRS2));
-set_fp_exceptions;
+++ /dev/null
-../../riscv/insns/fdiv_s.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fence.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/feq_d.h
\ No newline at end of file
+++ /dev/null
-require_fp;
-WRITE_RD(f32_eq(HFRS1, HFRS2));
-set_fp_exceptions;
+++ /dev/null
-../../riscv/insns/feq_s.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fld.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fle_d.h
\ No newline at end of file
+++ /dev/null
-require_fp;
-WRITE_RD(f32_le(HFRS1, HFRS2));
-set_fp_exceptions;
+++ /dev/null
-../../riscv/insns/fle_s.h
\ No newline at end of file
+++ /dev/null
-require_fp;
-WRITE_FRD(MMU.load_int16(RS1 + insn.i_imm()));
+++ /dev/null
-../../riscv/insns/flt_d.h
\ No newline at end of file
+++ /dev/null
-require_fp;
-WRITE_RD(f32_lt(HFRS1, HFRS2));
-set_fp_exceptions;
+++ /dev/null
-../../riscv/insns/flt_s.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/flw.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fmadd_d.h
\ No newline at end of file
+++ /dev/null
-require_fp;
-softfloat_roundingMode = RM;
-WRITE_HFRD(f32_mulAdd(HFRS1, HFRS2, HFRS3));
-set_fp_exceptions;
+++ /dev/null
-../../riscv/insns/fmadd_s.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fmax_d.h
\ No newline at end of file
+++ /dev/null
-require_fp;
-WRITE_HFRD(isNaNF32UI(HFRS2) || f32_le_quiet(HFRS2,HFRS1) /* && FRS1 not NaN */
- ? HFRS1 : HFRS2);
-set_fp_exceptions;
+++ /dev/null
-../../riscv/insns/fmax_s.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fmin_d.h
\ No newline at end of file
+++ /dev/null
-require_fp;
-WRITE_HFRD(isNaNF32UI(HFRS2) || f32_lt_quiet(HFRS1,HFRS2) /* && FRS1 not NaN */
- ? HFRS1 : HFRS2);
-set_fp_exceptions;
+++ /dev/null
-../../riscv/insns/fmin_s.h
\ No newline at end of file
+++ /dev/null
-if (RS1 & 0x1) WRITE_FRD(FRS2);
+++ /dev/null
-if (~RS1 & 0x1) WRITE_FRD(FRS2);
+++ /dev/null
-../../riscv/insns/fmsub_d.h
\ No newline at end of file
+++ /dev/null
-require_fp;
-softfloat_roundingMode = RM;
-WRITE_HFRD(f32_mulAdd(HFRS1, HFRS2, HFRS3 ^ (uint32_t)INT32_MIN));
-set_fp_exceptions;
+++ /dev/null
-../../riscv/insns/fmsub_s.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fmul_d.h
\ No newline at end of file
+++ /dev/null
-require_fp;
-softfloat_roundingMode = RM;
-WRITE_HFRD(f32_mulAdd(HFRS1, HFRS2, (HFRS1 ^ HFRS2) & (uint32_t)INT32_MIN));
-set_fp_exceptions;
+++ /dev/null
-../../riscv/insns/fmul_s.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fmv_d_x.h
\ No newline at end of file
+++ /dev/null
-require_fp;
-WRITE_FRD(RS1);
+++ /dev/null
-../../riscv/insns/fmv_s_x.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fmv_x_d.h
\ No newline at end of file
+++ /dev/null
-require_fp;
-WRITE_RD(sext16(FRS1));
+++ /dev/null
-../../riscv/insns/fmv_x_s.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fnmadd_d.h
\ No newline at end of file
+++ /dev/null
-require_fp;
-softfloat_roundingMode = RM;
-WRITE_HFRD(f32_mulAdd(HFRS1 ^ (uint32_t)INT32_MIN, HFRS2, HFRS3 ^ (uint32_t)INT32_MIN));
-set_fp_exceptions;
+++ /dev/null
-../../riscv/insns/fnmadd_s.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fnmsub_d.h
\ No newline at end of file
+++ /dev/null
-require_fp;
-softfloat_roundingMode = RM;
-WRITE_HFRD(f32_mulAdd(HFRS1 ^ (uint32_t)INT32_MIN, HFRS2, HFRS3));
-set_fp_exceptions;
+++ /dev/null
-../../riscv/insns/fnmsub_s.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fsd.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fsgnj_d.h
\ No newline at end of file
+++ /dev/null
-require_fp;
-WRITE_FRD((FRS1 &~ (uint16_t)INT16_MIN) | (FRS2 & (uint16_t)INT16_MIN));
+++ /dev/null
-../../riscv/insns/fsgnj_s.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fsgnjn_d.h
\ No newline at end of file
+++ /dev/null
-require_fp;
-WRITE_FRD((FRS1 &~ (uint32_t)INT32_MIN) | ((~FRS2) & (uint32_t)INT32_MIN));
+++ /dev/null
-../../riscv/insns/fsgnjn_s.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fsgnjx_d.h
\ No newline at end of file
+++ /dev/null
-require_fp;
-WRITE_FRD(FRS1 ^ (FRS2 & (uint16_t)INT16_MIN));
+++ /dev/null
-../../riscv/insns/fsgnjx_s.h
\ No newline at end of file
+++ /dev/null
-require_fp;
-MMU.store_uint16(RS1 + insn.s_imm(), FRS2);
+++ /dev/null
-../../riscv/insns/fsqrt_d.h
\ No newline at end of file
+++ /dev/null
-require_fp;
-softfloat_roundingMode = RM;
-WRITE_HFRD(f32_sqrt(HFRS1));
-set_fp_exceptions;
+++ /dev/null
-../../riscv/insns/fsqrt_s.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fsub_d.h
\ No newline at end of file
+++ /dev/null
-require_fp;
-softfloat_roundingMode = RM;
-WRITE_HFRD(f32_mulAdd(HFRS1, 0x3f800000, HFRS2 ^ (uint32_t)INT32_MIN));
-set_fp_exceptions;
+++ /dev/null
-../../riscv/insns/fsub_s.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/fsw.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/lb.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/lbu.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/ld.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/lh.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/lhu.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/lui.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/lw.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/lwu.h
\ No newline at end of file
+++ /dev/null
-if (RS1 & 0x1) WRITE_RD(RS2);
+++ /dev/null
-if (~RS1 & 0x1) WRITE_RD(RS2);
+++ /dev/null
-../../riscv/insns/mul.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/mulh.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/mulhsu.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/mulhu.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/mulw.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/or.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/ori.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/rem.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/remu.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/remuw.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/remw.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/sb.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/sd.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/sh.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/sll.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/slli.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/slliw.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/sllw.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/slt.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/slti.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/sltiu.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/sltu.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/sra.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/srai.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/sraiw.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/sraw.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/srl.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/srli.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/srliw.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/srlw.h
\ No newline at end of file
+++ /dev/null
-h->get_ut_state(UTIDX)->run = false;
+++ /dev/null
-../../riscv/insns/sub.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/subw.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/sw.h
\ No newline at end of file
+++ /dev/null
-WRITE_RD(UTIDX);
+++ /dev/null
-../../riscv/insns/xor.h
\ No newline at end of file
+++ /dev/null
-../../riscv/insns/xori.h
\ No newline at end of file
+++ /dev/null
-#include "encodings_hwacha.h"
-
-DECLARE_INSN(vf, MATCH_VF, MASK_VF)
-DECLARE_INSN(vflsegd, MATCH_VFLSEGD, MASK_VFLSEGD)
-DECLARE_INSN(vflsegstd, MATCH_VFLSEGSTD, MASK_VFLSEGSTD)
-DECLARE_INSN(vflsegstw, MATCH_VFLSEGSTW, MASK_VFLSEGSTW)
-DECLARE_INSN(vflsegw, MATCH_VFLSEGW, MASK_VFLSEGW)
-DECLARE_INSN(vfmsv_d, MATCH_VFMSV_D, MASK_VFMSV_D)
-DECLARE_INSN(vfmsv_s, MATCH_VFMSV_S, MASK_VFMSV_S)
-DECLARE_INSN(vfmvv, MATCH_VFMVV, MASK_VFMVV)
-DECLARE_INSN(vfssegd, MATCH_VFSSEGD, MASK_VFSSEGD)
-DECLARE_INSN(vfssegstd, MATCH_VFSSEGSTD, MASK_VFSSEGSTD)
-DECLARE_INSN(vfssegstw, MATCH_VFSSEGSTW, MASK_VFSSEGSTW)
-DECLARE_INSN(vfssegw, MATCH_VFSSEGW, MASK_VFSSEGW)
-DECLARE_INSN(vgetcfg, MATCH_VGETCFG, MASK_VGETCFG)
-DECLARE_INSN(vgetvl, MATCH_VGETVL, MASK_VGETVL)
-DECLARE_INSN(vlsegb, MATCH_VLSEGB, MASK_VLSEGB)
-DECLARE_INSN(vlsegbu, MATCH_VLSEGBU, MASK_VLSEGBU)
-DECLARE_INSN(vlsegd, MATCH_VLSEGD, MASK_VLSEGD)
-DECLARE_INSN(vlsegh, MATCH_VLSEGH, MASK_VLSEGH)
-DECLARE_INSN(vlseghu, MATCH_VLSEGHU, MASK_VLSEGHU)
-DECLARE_INSN(vlsegstb, MATCH_VLSEGSTB, MASK_VLSEGSTB)
-DECLARE_INSN(vlsegstbu, MATCH_VLSEGSTBU, MASK_VLSEGSTBU)
-DECLARE_INSN(vlsegstd, MATCH_VLSEGSTD, MASK_VLSEGSTD)
-DECLARE_INSN(vlsegsth, MATCH_VLSEGSTH, MASK_VLSEGSTH)
-DECLARE_INSN(vlsegsthu, MATCH_VLSEGSTHU, MASK_VLSEGSTHU)
-DECLARE_INSN(vlsegstw, MATCH_VLSEGSTW, MASK_VLSEGSTW)
-DECLARE_INSN(vlsegstwu, MATCH_VLSEGSTWU, MASK_VLSEGSTWU)
-DECLARE_INSN(vlsegw, MATCH_VLSEGW, MASK_VLSEGW)
-DECLARE_INSN(vlsegwu, MATCH_VLSEGWU, MASK_VLSEGWU)
-DECLARE_INSN(vmsv, MATCH_VMSV, MASK_VMSV)
-DECLARE_INSN(vmvv, MATCH_VMVV, MASK_VMVV)
-DECLARE_INSN(vsetcfg, MATCH_VSETCFG, MASK_VSETCFG)
-DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL)
-DECLARE_INSN(vssegb, MATCH_VSSEGB, MASK_VSSEGB)
-DECLARE_INSN(vssegd, MATCH_VSSEGD, MASK_VSSEGD)
-DECLARE_INSN(vssegh, MATCH_VSSEGH, MASK_VSSEGH)
-DECLARE_INSN(vssegstb, MATCH_VSSEGSTB, MASK_VSSEGSTB)
-DECLARE_INSN(vssegstd, MATCH_VSSEGSTD, MASK_VSSEGSTD)
-DECLARE_INSN(vssegsth, MATCH_VSSEGSTH, MASK_VSSEGSTH)
-DECLARE_INSN(vssegstw, MATCH_VSSEGSTW, MASK_VSSEGSTW)
-DECLARE_INSN(vssegw, MATCH_VSSEGW, MASK_VSSEGW)
-DECLARE_INSN(vxcptaux, MATCH_VXCPTAUX, MASK_VXCPTAUX)
-DECLARE_INSN(vxcptcause, MATCH_VXCPTCAUSE, MASK_VXCPTCAUSE)
-DECLARE_INSN(vxcptevac, MATCH_VXCPTEVAC, MASK_VXCPTEVAC)
-DECLARE_INSN(vxcpthold, MATCH_VXCPTHOLD, MASK_VXCPTHOLD)
-DECLARE_INSN(vxcptkill, MATCH_VXCPTKILL, MASK_VXCPTKILL)
+++ /dev/null
-DECLARE_INSN(ut_add, 0x33, 0xfe00707f)
-DECLARE_INSN(ut_addi, 0x13, 0x707f)
-DECLARE_INSN(ut_addiw, 0x1b, 0x707f)
-DECLARE_INSN(ut_addw, 0x3b, 0xfe00707f)
-DECLARE_INSN(ut_amoadd_d, 0x302f, 0xf800707f)
-DECLARE_INSN(ut_amoadd_w, 0x202f, 0xf800707f)
-DECLARE_INSN(ut_amoand_d, 0x6000302f, 0xf800707f)
-DECLARE_INSN(ut_amoand_w, 0x6000202f, 0xf800707f)
-DECLARE_INSN(ut_amomax_d, 0xa000302f, 0xf800707f)
-DECLARE_INSN(ut_amomaxu_d, 0xe000302f, 0xf800707f)
-DECLARE_INSN(ut_amomaxu_w, 0xe000202f, 0xf800707f)
-DECLARE_INSN(ut_amomax_w, 0xa000202f, 0xf800707f)
-DECLARE_INSN(ut_amomin_d, 0x8000302f, 0xf800707f)
-DECLARE_INSN(ut_amominu_d, 0xc000302f, 0xf800707f)
-DECLARE_INSN(ut_amominu_w, 0xc000202f, 0xf800707f)
-DECLARE_INSN(ut_amomin_w, 0x8000202f, 0xf800707f)
-DECLARE_INSN(ut_amoor_d, 0x4000302f, 0xf800707f)
-DECLARE_INSN(ut_amoor_w, 0x4000202f, 0xf800707f)
-DECLARE_INSN(ut_amoswap_d, 0x800302f, 0xf800707f)
-DECLARE_INSN(ut_amoswap_w, 0x800202f, 0xf800707f)
-DECLARE_INSN(ut_amoxor_d, 0x2000302f, 0xf800707f)
-DECLARE_INSN(ut_amoxor_w, 0x2000202f, 0xf800707f)
-DECLARE_INSN(ut_and, 0x7033, 0xfe00707f)
-DECLARE_INSN(ut_andi, 0x7013, 0x707f)
-DECLARE_INSN(ut_auipc, 0x17, 0x7f)
-DECLARE_INSN(ut_div, 0x2004033, 0xfe00707f)
-DECLARE_INSN(ut_divu, 0x2005033, 0xfe00707f)
-DECLARE_INSN(ut_divuw, 0x200503b, 0xfe00707f)
-DECLARE_INSN(ut_divw, 0x200403b, 0xfe00707f)
-DECLARE_INSN(ut_fadd_d, 0x2000053, 0xfe00007f)
-DECLARE_INSN(ut_fadd_h, 0x4000053, 0xfe00007f)
-DECLARE_INSN(ut_fadd_s, 0x53, 0xfe00007f)
-DECLARE_INSN(ut_fclass_d, 0xe2001053, 0xfff0707f)
-DECLARE_INSN(ut_fclass_s, 0xe0001053, 0xfff0707f)
-DECLARE_INSN(ut_fcvt_d_h, 0x8c000053, 0xfff0007f)
-DECLARE_INSN(ut_fcvt_d_l, 0xd2200053, 0xfff0007f)
-DECLARE_INSN(ut_fcvt_d_lu, 0xd2300053, 0xfff0007f)
-DECLARE_INSN(ut_fcvt_d_s, 0x42000053, 0xfff0007f)
-DECLARE_INSN(ut_fcvt_d_w, 0xd2000053, 0xfff0007f)
-DECLARE_INSN(ut_fcvt_d_wu, 0xd2100053, 0xfff0007f)
-DECLARE_INSN(ut_fcvt_h_d, 0x92000053, 0xfff0007f)
-DECLARE_INSN(ut_fcvt_h_l, 0x64000053, 0xfff0007f)
-DECLARE_INSN(ut_fcvt_h_lu, 0x6c000053, 0xfff0007f)
-DECLARE_INSN(ut_fcvt_h_s, 0x90000053, 0xfff0007f)
-DECLARE_INSN(ut_fcvt_h_w, 0x74000053, 0xfff0007f)
-DECLARE_INSN(ut_fcvt_h_wu, 0x7c000053, 0xfff0007f)
-DECLARE_INSN(ut_fcvt_l_d, 0xc2200053, 0xfff0007f)
-DECLARE_INSN(ut_fcvt_l_h, 0x44000053, 0xfff0007f)
-DECLARE_INSN(ut_fcvt_l_s, 0xc0200053, 0xfff0007f)
-DECLARE_INSN(ut_fcvt_lu_d, 0xc2300053, 0xfff0007f)
-DECLARE_INSN(ut_fcvt_lu_h, 0x4c000053, 0xfff0007f)
-DECLARE_INSN(ut_fcvt_lu_s, 0xc0300053, 0xfff0007f)
-DECLARE_INSN(ut_fcvt_s_d, 0x40100053, 0xfff0007f)
-DECLARE_INSN(ut_fcvt_s_h, 0x84000053, 0xfff0007f)
-DECLARE_INSN(ut_fcvt_s_l, 0xd0200053, 0xfff0007f)
-DECLARE_INSN(ut_fcvt_s_lu, 0xd0300053, 0xfff0007f)
-DECLARE_INSN(ut_fcvt_s_w, 0xd0000053, 0xfff0007f)
-DECLARE_INSN(ut_fcvt_s_wu, 0xd0100053, 0xfff0007f)
-DECLARE_INSN(ut_fcvt_w_d, 0xc2000053, 0xfff0007f)
-DECLARE_INSN(ut_fcvt_w_h, 0x54000053, 0xfff0007f)
-DECLARE_INSN(ut_fcvt_w_s, 0xc0000053, 0xfff0007f)
-DECLARE_INSN(ut_fcvt_wu_d, 0xc2100053, 0xfff0007f)
-DECLARE_INSN(ut_fcvt_wu_h, 0x5c000053, 0xfff0007f)
-DECLARE_INSN(ut_fcvt_wu_s, 0xc0100053, 0xfff0007f)
-DECLARE_INSN(ut_fdiv_d, 0x1a000053, 0xfe00007f)
-DECLARE_INSN(ut_fdiv_h, 0x1c000053, 0xfe00007f)
-DECLARE_INSN(ut_fdiv_s, 0x18000053, 0xfe00007f)
-DECLARE_INSN(ut_fence, 0xf, 0x707f)
-DECLARE_INSN(ut_feq_d, 0xa2002053, 0xfe00707f)
-DECLARE_INSN(ut_feq_h, 0xac000053, 0xfe00707f)
-DECLARE_INSN(ut_feq_s, 0xa0002053, 0xfe00707f)
-DECLARE_INSN(ut_fld, 0x3007, 0x707f)
-DECLARE_INSN(ut_fle_d, 0xa2000053, 0xfe00707f)
-DECLARE_INSN(ut_fle_h, 0xbc000053, 0xfe00707f)
-DECLARE_INSN(ut_fle_s, 0xa0000053, 0xfe00707f)
-DECLARE_INSN(ut_flh, 0x1007, 0x707f)
-DECLARE_INSN(ut_flt_d, 0xa2001053, 0xfe00707f)
-DECLARE_INSN(ut_flt_h, 0xb4000053, 0xfe00707f)
-DECLARE_INSN(ut_flt_s, 0xa0001053, 0xfe00707f)
-DECLARE_INSN(ut_flw, 0x2007, 0x707f)
-DECLARE_INSN(ut_fmadd_d, 0x2000043, 0x600007f)
-DECLARE_INSN(ut_fmadd_h, 0x4000043, 0x600007f)
-DECLARE_INSN(ut_fmadd_s, 0x43, 0x600007f)
-DECLARE_INSN(ut_fmax_d, 0x2a001053, 0xfe00707f)
-DECLARE_INSN(ut_fmax_h, 0xcc000053, 0xfe00707f)
-DECLARE_INSN(ut_fmax_s, 0x28001053, 0xfe00707f)
-DECLARE_INSN(ut_fmin_d, 0x2a000053, 0xfe00707f)
-DECLARE_INSN(ut_fmin_h, 0xc4000053, 0xfe00707f)
-DECLARE_INSN(ut_fmin_s, 0x28000053, 0xfe00707f)
-DECLARE_INSN(ut_fmovn, 0x6007077, 0xfe00707f)
-DECLARE_INSN(ut_fmovz, 0x4007077, 0xfe00707f)
-DECLARE_INSN(ut_fmsub_d, 0x2000047, 0x600007f)
-DECLARE_INSN(ut_fmsub_h, 0x4000047, 0x600007f)
-DECLARE_INSN(ut_fmsub_s, 0x47, 0x600007f)
-DECLARE_INSN(ut_fmul_d, 0x12000053, 0xfe00007f)
-DECLARE_INSN(ut_fmul_h, 0x14000053, 0xfe00007f)
-DECLARE_INSN(ut_fmul_s, 0x10000053, 0xfe00007f)
-DECLARE_INSN(ut_fmv_d_x, 0xf2000053, 0xfff0707f)
-DECLARE_INSN(ut_fmv_h_x, 0xf4000053, 0xfff0707f)
-DECLARE_INSN(ut_fmv_s_x, 0xf0000053, 0xfff0707f)
-DECLARE_INSN(ut_fmv_x_d, 0xe2000053, 0xfff0707f)
-DECLARE_INSN(ut_fmv_x_h, 0xe4000053, 0xfff0707f)
-DECLARE_INSN(ut_fmv_x_s, 0xe0000053, 0xfff0707f)
-DECLARE_INSN(ut_fnmadd_d, 0x200004f, 0x600007f)
-DECLARE_INSN(ut_fnmadd_h, 0x400004f, 0x600007f)
-DECLARE_INSN(ut_fnmadd_s, 0x4f, 0x600007f)
-DECLARE_INSN(ut_fnmsub_d, 0x200004b, 0x600007f)
-DECLARE_INSN(ut_fnmsub_h, 0x400004b, 0x600007f)
-DECLARE_INSN(ut_fnmsub_s, 0x4b, 0x600007f)
-DECLARE_INSN(ut_fsd, 0x3027, 0x707f)
-DECLARE_INSN(ut_fsgnj_d, 0x22000053, 0xfe00707f)
-DECLARE_INSN(ut_fsgnj_h, 0x2c000053, 0xfe00707f)
-DECLARE_INSN(ut_fsgnjn_d, 0x22001053, 0xfe00707f)
-DECLARE_INSN(ut_fsgnjn_h, 0x34000053, 0xfe00707f)
-DECLARE_INSN(ut_fsgnjn_s, 0x20001053, 0xfe00707f)
-DECLARE_INSN(ut_fsgnj_s, 0x20000053, 0xfe00707f)
-DECLARE_INSN(ut_fsgnjx_d, 0x22002053, 0xfe00707f)
-DECLARE_INSN(ut_fsgnjx_h, 0x3c000053, 0xfe00707f)
-DECLARE_INSN(ut_fsgnjx_s, 0x20002053, 0xfe00707f)
-DECLARE_INSN(ut_fsh, 0x1027, 0x707f)
-DECLARE_INSN(ut_fsqrt_d, 0x5a000053, 0xfff0007f)
-DECLARE_INSN(ut_fsqrt_h, 0x24000053, 0xfff0007f)
-DECLARE_INSN(ut_fsqrt_s, 0x58000053, 0xfff0007f)
-DECLARE_INSN(ut_fsub_d, 0xa000053, 0xfe00007f)
-DECLARE_INSN(ut_fsub_h, 0xc000053, 0xfe00007f)
-DECLARE_INSN(ut_fsub_s, 0x8000053, 0xfe00007f)
-DECLARE_INSN(ut_fsw, 0x2027, 0x707f)
-DECLARE_INSN(ut_lb, 0x3, 0x707f)
-DECLARE_INSN(ut_lbu, 0x4003, 0x707f)
-DECLARE_INSN(ut_ld, 0x3003, 0x707f)
-DECLARE_INSN(ut_lh, 0x1003, 0x707f)
-DECLARE_INSN(ut_lhu, 0x5003, 0x707f)
-DECLARE_INSN(ut_lui, 0x37, 0x7f)
-DECLARE_INSN(ut_lw, 0x2003, 0x707f)
-DECLARE_INSN(ut_lwu, 0x6003, 0x707f)
-DECLARE_INSN(ut_movn, 0x2007077, 0xfe00707f)
-DECLARE_INSN(ut_movz, 0x7077, 0xfe00707f)
-DECLARE_INSN(ut_mul, 0x2000033, 0xfe00707f)
-DECLARE_INSN(ut_mulh, 0x2001033, 0xfe00707f)
-DECLARE_INSN(ut_mulhsu, 0x2002033, 0xfe00707f)
-DECLARE_INSN(ut_mulhu, 0x2003033, 0xfe00707f)
-DECLARE_INSN(ut_mulw, 0x200003b, 0xfe00707f)
-DECLARE_INSN(ut_or, 0x6033, 0xfe00707f)
-DECLARE_INSN(ut_ori, 0x6013, 0x707f)
-DECLARE_INSN(ut_rem, 0x2006033, 0xfe00707f)
-DECLARE_INSN(ut_remu, 0x2007033, 0xfe00707f)
-DECLARE_INSN(ut_remuw, 0x200703b, 0xfe00707f)
-DECLARE_INSN(ut_remw, 0x200603b, 0xfe00707f)
-DECLARE_INSN(ut_sb, 0x23, 0x707f)
-DECLARE_INSN(ut_sd, 0x3023, 0x707f)
-DECLARE_INSN(ut_sh, 0x1023, 0x707f)
-DECLARE_INSN(ut_sll, 0x1033, 0xfe00707f)
-DECLARE_INSN(ut_slli, 0x1013, 0xfc00707f)
-DECLARE_INSN(ut_slliw, 0x101b, 0xfe00707f)
-DECLARE_INSN(ut_sllw, 0x103b, 0xfe00707f)
-DECLARE_INSN(ut_slt, 0x2033, 0xfe00707f)
-DECLARE_INSN(ut_slti, 0x2013, 0x707f)
-DECLARE_INSN(ut_sltiu, 0x3013, 0x707f)
-DECLARE_INSN(ut_sltu, 0x3033, 0xfe00707f)
-DECLARE_INSN(ut_sra, 0x40005033, 0xfe00707f)
-DECLARE_INSN(ut_srai, 0x40005013, 0xfc00707f)
-DECLARE_INSN(ut_sraiw, 0x4000501b, 0xfe00707f)
-DECLARE_INSN(ut_sraw, 0x4000503b, 0xfe00707f)
-DECLARE_INSN(ut_srl, 0x5033, 0xfe00707f)
-DECLARE_INSN(ut_srli, 0x5013, 0xfc00707f)
-DECLARE_INSN(ut_srliw, 0x501b, 0xfe00707f)
-DECLARE_INSN(ut_srlw, 0x503b, 0xfe00707f)
-DECLARE_INSN(ut_stop, 0x5077, 0xffffffff)
-DECLARE_INSN(ut_sub, 0x40000033, 0xfe00707f)
-DECLARE_INSN(ut_subw, 0x4000003b, 0xfe00707f)
-DECLARE_INSN(ut_sw, 0x2023, 0x707f)
-DECLARE_INSN(ut_utidx, 0x6077, 0xfffff07f)
-DECLARE_INSN(ut_xor, 0x4033, 0xfe00707f)
-DECLARE_INSN(ut_xori, 0x4013, 0x707f)
+++ /dev/null
-prefix=@prefix@
-exec_prefix=@prefix@
-libdir=${prefix}/@libdir@
-includedir=${prefix}/@includedir@
-
-Name: riscv-hwacha
-Description: RISC-V Hwacha binary library
-Version: git
-Libs: -Wl,-rpath,${libdir} -L${libdir} -lhwacha
-Cflags: -I${includedir}
-URL: http://riscv.org/download.html#tab_spike
Name: riscv-spike
Description: RISC-V spike meta library
Version: git
-Depends: riscv-spike_main riscv-riscv riscv-hwacha riscv-softfloat
+Depends: riscv-spike_main riscv-riscv riscv-softfloat
URL: http://riscv.org/download.html#tab_spike
Name: riscv-spike_main
Description: RISC-V ISA simulator library
Version: git
-Depends: riscv-riscv riscv-hwacha riscv-softfloat
+Depends: riscv-riscv riscv-softfloat
Libs: -Wl,-rpath,${libdir} -L${libdir} -lspike_main
Cflags: -I${includedir}
URL: http://riscv.org/download.html#tab_spike
projects / riscv-isa-sim.git / commitdiff