{"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}},
+/* or 1,1,1 */
+{"cctpl", 0x7c210b78, 0xffffffff, CELL, 0, {0}},
+/* or 2,2,2 */
+{"cctpm", 0x7c421378, 0xffffffff, CELL, 0, {0}},
+/* or 3,3,3 */
+{"cctph", 0x7c631b78, 0xffffffff, CELL, 0, {0}},
/* or 26,26,26 */
{"miso", 0x7f5ad378, 0xffffffff, POWER8|E6500, 0, {0}},
/* or 27,27,27 */
{"mdoio", 0x7fbdeb78, 0xffffffff, POWER7, 0, {0}},
/* or 30,30,30 */
{"mdoom", 0x7fdef378, 0xffffffff, POWER7, 0, {0}},
+
{"mr", XRC(31,444,0), X_MASK, COM, 0, {RA, RSB}},
{"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}},
{"mr.", XRC(31,444,1), X_MASK, COM, 0, {RA, RSB}},
{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}},
-{"cctpl", 0x7c210b78, 0xffffffff, CELL, 0, {0}},
-{"cctpm", 0x7c421378, 0xffffffff, CELL, 0, {0}},
-{"cctph", 0x7c631b78, 0xffffffff, CELL, 0, {0}},
-
{"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
{"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
{"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, 0, {0}},