gas:

2009-01-29  Mark Mitchell  <mark@codesourcery.com>

	* config/tc-arm.c (insns): Correct encoding of qadd, qdadd, qsub,
	qdsub in Thumb-2 mode.

gas/testsuite:
2009-01-29  Mark Mitchell  <mark@codesourcery.com>

	* gas/arm/thumb32.s (qadd): Add qadd, qdadd, qsub, and qdsub.
	* gas/arm/thumb32.d: Likewise.

opcodes:
2009-01-29  Mark Mitchell  <mark@codesourcery.com>

	* arm-dis.c (thumb32_opcodes): Correct decoding for qadd, qdadd,
	qsub, and qdsub.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 4cf790177ec36cc74b75d903241c087aa6d2f289..cc855cd137e74f26a80cccbb9b6967d2d4a0d93b 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2009-01-29  Mark Mitchell  <mark@codesourcery.com>
+
+       * config/tc-arm.c (insns): Correct encoding of qadd, qdadd, qsub,
+       qdsub in Thumb-2 mode.
+
 2009-01-29  Paul Brook  <paul@codesourcery.com>
             Mark Mitchell  <mark@codesourcery.com>
 

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index f7bca73c64b6608ce85c88362669aebdb59dd080..0d4d005da241baa62fb711c16f09aef115ca98be 100644 (file)
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -15232,10 +15232,10 @@ static const struct asm_opcode insns[] =
  TCE(smulwb,   12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc),        smul, t_simd),
  TCE(smulwt,   12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc),        smul, t_simd),
 
- TCE(qadd,     1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc),        rd_rm_rn, rd_rm_rn),
- TCE(qdadd,    1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc),        rd_rm_rn, rd_rm_rn),
- TCE(qsub,     1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc),        rd_rm_rn, rd_rm_rn),
- TCE(qdsub,    1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc),        rd_rm_rn, rd_rm_rn),
+ TCE(qadd,     1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc),        rd_rm_rn, t_simd),
+ TCE(qdadd,    1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc),        rd_rm_rn, t_simd),
+ TCE(qsub,     1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc),        rd_rm_rn, t_simd),
+ TCE(qdsub,    1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc),        rd_rm_rn, t_simd),
 
 #undef ARM_VARIANT
 #define ARM_VARIANT &arm_ext_v5e /*  ARM Architecture 5TE.  */

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 034ce59aedc9644d3d07674ffadf24c14a31093c..7bc3d8e232974e7b784fca267a8aa236f8baefc4 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2009-01-29  Mark Mitchell  <mark@codesourcery.com>
+
+       * gas/arm/thumb32.s (qadd): Add qadd, qdadd, qsub, and qdsub.
+       * gas/arm/thumb32.d: Likewise.
+
 2009-01-29  Paul Brook  <paul@codesourcery.com>
             Mark Mitchell  <mark@codesourcery.com>
 

diff --git a/gas/testsuite/gas/arm/thumb32.d b/gas/testsuite/gas/arm/thumb32.d
index 1930e8954f43f868ef4fc99af74149e2ab268b96..406100ce3ba7a995929b17a67812575b6994bdae 100644 (file)
--- a/gas/testsuite/gas/arm/thumb32.d
+++ b/gas/testsuite/gas/arm/thumb32.d
@@ -682,9 +682,13 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> bd02        pop     \{r1, pc\}
 0[0-9a-f]+ <[^>]+> e92d 1f00   stmdb   sp!, \{r8, r9, sl, fp, ip\}
 0[0-9a-f]+ <[^>]+> e8bd 1f00   ldmia\.w        sp!, \{r8, r9, sl, fp, ip\}
+0[0-9a-f]+ <[^>]+> fa82 f183   qadd    r1, r2, r3
 0[0-9a-f]+ <[^>]+> fa92 f113   qadd16  r1, r2, r3
 0[0-9a-f]+ <[^>]+> fa82 f113   qadd8   r1, r2, r3
 0[0-9a-f]+ <[^>]+> faa2 f113   qaddsubx        r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa82 f193   qdadd   r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa82 f1b3   qdsub   r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa82 f1a3   qsub    r1, r2, r3
 0[0-9a-f]+ <[^>]+> fad2 f113   qsub16  r1, r2, r3
 0[0-9a-f]+ <[^>]+> fac2 f113   qsub8   r1, r2, r3
 0[0-9a-f]+ <[^>]+> fae2 f113   qsubaddx        r1, r2, r3
@@ -913,26 +917,26 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> fa52 f183   uxtab   r1, r2, r3
 0[0-9a-f]+ <[^>]+> fa32 f183   uxtab16 r1, r2, r3
 0[0-9a-f]+ <[^>]+> fa12 f183   uxtah   r1, r2, r3
-0[0-9a-f]+ <[^>]+> f89f 12aa   ldrb\.w r1, \[pc, #682\]        ; 0+e02 <[^>]+>
-0[0-9a-f]+ <[^>]+> f89f 1155   ldrb\.w r1, \[pc, #341\]        ; 0+cb1 <[^>]+>
-0[0-9a-f]+ <[^>]+> f81f 12aa   ldrb\.w r1, \[pc, #-682\]       ; 0+8b6 <[^>]+>
-0[0-9a-f]+ <[^>]+> f81f 1155   ldrb\.w r1, \[pc, #-341\]       ; 0+a0f <[^>]+>
-0[0-9a-f]+ <[^>]+> f99f 12aa   ldrsb\.w        r1, \[pc, #682\]        ; 0+e12 <[^>]+>
-0[0-9a-f]+ <[^>]+> f99f 1155   ldrsb\.w        r1, \[pc, #341\]        ; 0+cc1 <[^>]+>
-0[0-9a-f]+ <[^>]+> f91f 12aa   ldrsb\.w        r1, \[pc, #-682\]       ; 0+8c6 <[^>]+>
-0[0-9a-f]+ <[^>]+> f91f 1155   ldrsb\.w        r1, \[pc, #-341\]       ; 0+a1f <[^>]+>
-0[0-9a-f]+ <[^>]+> f8bf 12aa   ldrh\.w r1, \[pc, #682\]        ; 0+e22 <[^>]+>
-0[0-9a-f]+ <[^>]+> f8bf 1155   ldrh\.w r1, \[pc, #341\]        ; 0+cd1 <[^>]+>
-0[0-9a-f]+ <[^>]+> f83f 12aa   ldrh\.w r1, \[pc, #-682\]       ; 0+8d6 <[^>]+>
-0[0-9a-f]+ <[^>]+> f83f 1155   ldrh\.w r1, \[pc, #-341\]       ; 0+a2f <[^>]+>
-0[0-9a-f]+ <[^>]+> f9bf 12aa   ldrsh\.w        r1, \[pc, #682\]        ; 0+e32 <[^>]+>
-0[0-9a-f]+ <[^>]+> f9bf 1155   ldrsh\.w        r1, \[pc, #341\]        ; 0+ce1 <[^>]+>
-0[0-9a-f]+ <[^>]+> f93f 12aa   ldrsh\.w        r1, \[pc, #-682\]       ; 0+8e6 <[^>]+>
-0[0-9a-f]+ <[^>]+> f93f 1155   ldrsh\.w        r1, \[pc, #-341\]       ; 0+a3f <[^>]+>
-0[0-9a-f]+ <[^>]+> f8df 12aa   ldr\.w  r1, \[pc, #682\]        ; 0+e42 <[^>]+>
-0[0-9a-f]+ <[^>]+> f8df 1155   ldr\.w  r1, \[pc, #341\]        ; 0+cf1 <[^>]+>
-0[0-9a-f]+ <[^>]+> f85f 12aa   ldr\.w  r1, \[pc, #-682\]       ; 0+8f6 <[^>]+>
-0[0-9a-f]+ <[^>]+> f85f 1155   ldr\.w  r1, \[pc, #-341\]       ; 0+a4f <[^>]+>
+0[0-9a-f]+ <[^>]+> f89f 12aa   ldrb\.w r1, \[pc, #682\]        ; 0+e12 <[^>]+>
+0[0-9a-f]+ <[^>]+> f89f 1155   ldrb\.w r1, \[pc, #341\]        ; 0+cc1 <[^>]+>
+0[0-9a-f]+ <[^>]+> f81f 12aa   ldrb\.w r1, \[pc, #-682\]       ; 0+8c6 <[^>]+>
+0[0-9a-f]+ <[^>]+> f81f 1155   ldrb\.w r1, \[pc, #-341\]       ; 0+a1f <[^>]+>
+0[0-9a-f]+ <[^>]+> f99f 12aa   ldrsb\.w        r1, \[pc, #682\]        ; 0+e22 <[^>]+>
+0[0-9a-f]+ <[^>]+> f99f 1155   ldrsb\.w        r1, \[pc, #341\]        ; 0+cd1 <[^>]+>
+0[0-9a-f]+ <[^>]+> f91f 12aa   ldrsb\.w        r1, \[pc, #-682\]       ; 0+8d6 <[^>]+>
+0[0-9a-f]+ <[^>]+> f91f 1155   ldrsb\.w        r1, \[pc, #-341\]       ; 0+a2f <[^>]+>
+0[0-9a-f]+ <[^>]+> f8bf 12aa   ldrh\.w r1, \[pc, #682\]        ; 0+e32 <[^>]+>
+0[0-9a-f]+ <[^>]+> f8bf 1155   ldrh\.w r1, \[pc, #341\]        ; 0+ce1 <[^>]+>
+0[0-9a-f]+ <[^>]+> f83f 12aa   ldrh\.w r1, \[pc, #-682\]       ; 0+8e6 <[^>]+>
+0[0-9a-f]+ <[^>]+> f83f 1155   ldrh\.w r1, \[pc, #-341\]       ; 0+a3f <[^>]+>
+0[0-9a-f]+ <[^>]+> f9bf 12aa   ldrsh\.w        r1, \[pc, #682\]        ; 0+e42 <[^>]+>
+0[0-9a-f]+ <[^>]+> f9bf 1155   ldrsh\.w        r1, \[pc, #341\]        ; 0+cf1 <[^>]+>
+0[0-9a-f]+ <[^>]+> f93f 12aa   ldrsh\.w        r1, \[pc, #-682\]       ; 0+8f6 <[^>]+>
+0[0-9a-f]+ <[^>]+> f93f 1155   ldrsh\.w        r1, \[pc, #-341\]       ; 0+a4f <[^>]+>
+0[0-9a-f]+ <[^>]+> f8df 12aa   ldr\.w  r1, \[pc, #682\]        ; 0+e52 <[^>]+>
+0[0-9a-f]+ <[^>]+> f8df 1155   ldr\.w  r1, \[pc, #341\]        ; 0+d01 <[^>]+>
+0[0-9a-f]+ <[^>]+> f85f 12aa   ldr\.w  r1, \[pc, #-682\]       ; 0+906 <[^>]+>
+0[0-9a-f]+ <[^>]+> f85f 1155   ldr\.w  r1, \[pc, #-341\]       ; 0+a5f <[^>]+>
 0[0-9a-f]+ <[^>]+> f200 0900   addw    r9, r0, #0      ; 0x0
 0[0-9a-f]+ <[^>]+> f60f 76ff   addw    r6, pc, #4095   ; 0xfff
 0[0-9a-f]+ <[^>]+> f6a9 2685   subw    r6, r9, #2693   ; 0xa85

diff --git a/gas/testsuite/gas/arm/thumb32.s b/gas/testsuite/gas/arm/thumb32.s
index 697dfd240f3481ff9ed5cfbcd00f712f398932dd..a4653d083d82f421ecc87b94479e33cbde24d5c8 100644 (file)
--- a/gas/testsuite/gas/arm/thumb32.s
+++ b/gas/testsuite/gas/arm/thumb32.s
@@ -526,9 +526,13 @@ push_pop:
        pop     {r8,r9,r10,r11,r12}
 
 qadd:
+       qadd            r1, r2, r3
        qadd16          r1, r2, r3
        qadd8           r1, r2, r3
        qaddsubx        r1, r2, r3
+       qdadd           r1, r2, r3
+       qdsub           r1, r2, r3
+       qsub            r1, r2, r3
        qsub16          r1, r2, r3
        qsub8           r1, r2, r3
        qsubaddx        r1, r2, r3

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 402cece65105797950b31425636f8b85ea126185..7466da19ab1fa53f7bb3444cbad6d4cc35d76257 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2009-01-29  Mark Mitchell  <mark@codesourcery.com>
+
+       * arm-dis.c (thumb32_opcodes): Correct decoding for qadd, qdadd,
+       qsub, and qdsub.
+
 2009-01-28  Chao-ying Fu  <fu@mips.com>
 
         * mips-opc.c (suxc1): Add the flag of FP_D.

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index f462143eb354e805cb600fa791ddb06d6bdac415..44c2383cab3f5c13a9b5002f5ee2f92396307a9c 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -1280,10 +1280,10 @@ static const struct opcode32 thumb32_opcodes[] =
   {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
   {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
   {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
-  {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
-  {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
-  {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
-  {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
+  {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %16-19r, %0-3r"},
+  {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %16-19r, %0-3r"},
+  {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %16-19r, %0-3r"},
+  {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %16-19r, %0-3r"},
   {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
   {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
   {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},