Fix 48262

Co-Authored-By: Michael Meissner <meissner@linux.vnet.ibm.com>
From-SVN: r171847

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index bfaf388b089c3bc669a62a5e006269e1a1ec8705..09091ea6b55af550ab3f56f61f5b10c1e1eca2ad 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,16 @@
+2011-04-01  Andrew Pinski  <pinskia@gmail.com>
+           Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+       PR target/48262
+       * config/rs6000/vector.md (movmisalign<mode>): Allow for memory
+       operands, as per the specifications.
+
+       * config/rs6000/altivec.md (vec_extract_evenv4si): Correct modes.
+       (vec_extract_evenv4sf): Ditto.
+       (vec_extract_evenv8hi): Ditto.
+       (vec_extract_evenv16qi): Ditto.
+       (vec_extract_oddv4si): Ditto.
+
 2011-03-31  Mark Wielaard  <mjw@redhat.com>
 
        * dwarf2out.c (dwarf2out_finish): Don't add low_pc and/or

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index d507b86973f43bd788d267cace35326fbeef4762..5e803f61727c215038f1d42b659432bbef2425a4 100644 (file)
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -2422,7 +2422,7 @@
 
 (define_expand "vec_extract_evenv4si"
  [(set (match_operand:V4SI 0 "register_operand" "")
-        (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "")
+        (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "")
                       (match_operand:V4SI 2 "register_operand" "")]
                      UNSPEC_EXTEVEN_V4SI))]
   "TARGET_ALTIVEC"
@@ -2455,7 +2455,7 @@
 
 (define_expand "vec_extract_evenv4sf"
  [(set (match_operand:V4SF 0 "register_operand" "")
-        (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "")
+        (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "")
                       (match_operand:V4SF 2 "register_operand" "")]
                       UNSPEC_EXTEVEN_V4SF))]
   "TARGET_ALTIVEC"
@@ -2487,7 +2487,7 @@
 }")
 
 (define_expand "vec_extract_evenv8hi"
- [(set (match_operand:V4SI 0 "register_operand" "")
+ [(set (match_operand:V8HI 0 "register_operand" "")
         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "")
                       (match_operand:V8HI 2 "register_operand" "")]
                       UNSPEC_EXTEVEN_V8HI))]
@@ -2520,9 +2520,9 @@
 }")
 
 (define_expand "vec_extract_evenv16qi"
- [(set (match_operand:V4SI 0 "register_operand" "")
-        (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "")
-                      (match_operand:V16QI 2 "register_operand" "")]
+ [(set (match_operand:V16QI 0 "register_operand" "")
+        (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "")
+                       (match_operand:V16QI 2 "register_operand" "")]
                       UNSPEC_EXTEVEN_V16QI))]
   "TARGET_ALTIVEC"
   "
@@ -2554,7 +2554,7 @@
 
 (define_expand "vec_extract_oddv4si"
  [(set (match_operand:V4SI 0 "register_operand" "")
-        (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "")
+        (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "")
                       (match_operand:V4SI 2 "register_operand" "")]
                       UNSPEC_EXTODD_V4SI))]
   "TARGET_ALTIVEC"
@@ -2587,7 +2587,7 @@
 
 (define_expand "vec_extract_oddv4sf"
  [(set (match_operand:V4SF 0 "register_operand" "")
-        (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "")
+        (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "")
                       (match_operand:V4SF 2 "register_operand" "")]
                       UNSPEC_EXTODD_V4SF))]
   "TARGET_ALTIVEC"

diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index c5a7870a5c7d8b5bd3853bcb4f96d237788f5b05..a3a8e124dd37e7ce2af6f777b8694cc8dff0ca09 100644 (file)
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -871,8 +871,8 @@
 ;; Under VSX, vectors of 4/8 byte alignments do not need to be aligned
 ;; since the load already handles it.
 (define_expand "movmisalign<mode>"
- [(set (match_operand:VEC_N 0 "vfloat_operand" "")
-       (match_operand:VEC_N 1 "vfloat_operand" ""))]
+ [(set (match_operand:VEC_N 0 "nonimmediate_operand" "")
+       (match_operand:VEC_N 1 "any_operand" ""))]
  "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_ALLOW_MOVMISALIGN"
  "")