pan/midgard: Dynamically allocate r26/27 for spills
authorAlyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fri, 6 Dec 2019 17:20:31 +0000 (12:20 -0500)
committerAlyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Thu, 12 Dec 2019 16:42:07 +0000 (11:42 -0500)
This allows us to spill two 128-bit values in the same bundle, since we
have two registers we can spill with. This improves the
register allocation flexibility in programs with heavy spilling, though
unfortunately it isn't sufficient (theoretically, 3.5 128-bit values can
be spilled from 3 vector units and 2 scalar units).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
src/panfrost/midgard/compiler.h
src/panfrost/midgard/midgard_ra.c

index eb0464e6a49f45f9ba2d64970ca9de8b8b4f885c..a6facae4422839071b1d32169f45d3edabea84ee 100644 (file)
@@ -598,12 +598,17 @@ v_load_store_scratch(
         ins.constants[0] = byte;
 
         if (is_store) {
-                /* r0 = r26, r1 = r27 */
-                assert(srcdest == SSA_FIXED_REGISTER(26) || srcdest == SSA_FIXED_REGISTER(27));
                 ins.src[0] = srcdest;
-        } else {
+
+                /* Ensure we are tightly swizzled so liveness analysis is
+                 * correct */
+
+                for (unsigned i = 0; i < 4; ++i) {
+                        if (!(mask & (1 << i)))
+                                ins.swizzle[0][i] = COMPONENT_X;
+                }
+        } else
                 ins.dest = srcdest;
-        }
 
         return ins;
 }
index 56d1f277d5f0718bcbefac8bbe88ceb91fedf75c..d5cfd6214a25c1f4ea1eb633e925b9ff770c098a 100644 (file)
@@ -738,7 +738,7 @@ mir_spill_register(
                                 st = v_mov(spill_node, spill_slot);
                                 st.no_spill = true;
                         } else {
-                                ins->dest = SSA_FIXED_REGISTER(26);
+                                ins->dest = spill_index++;
                                 ins->no_spill = true;
                                 st = v_load_store_scratch(ins->dest, spill_slot, true, ins->mask);
                         }