x86: Invalidating TLB entry on page fault

As per the x86 architecture specification, matching TLB entries need to be
invalidated on a page fault. For instance, after a page fault due to inadequate
protection bits on a TLB hit, the TLB entry needs to be invalidated. This
behavior is clearly specified in the x86 architecture manuals from both AMD and
Intel.  This invalidation is missing currently in gem5, due to which linux
kernel versions 3.8 and up cannot be simulated efficiently. This is exposed by
a linux optimisation in commit e4a1cc56e4d728eb87072c71c07581524e5160b1, which
removes a tlb flush on updating page table entries in x86.

Testing: Linux kernel versions 3.8 onwards were booting very slowly in FS mode,
due to repeated page faults (~300000 before the first print statement in a
bash file). Ensured that page fault rate drops drastically and observed
reduction in boot time from order of hours to minutes for linux kernel v3.8
and v3.11

diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc
index e3a4befb2533ff076771cf0b9fb28ab59740490c..b7d9335d45a8c25d6cf67de51bd9d623cef4f8d3 100644 (file)
--- a/src/arch/x86/faults.cc
+++ b/src/arch/x86/faults.cc
@@ -135,6 +135,9 @@ namespace X86ISA
     void PageFault::invoke(ThreadContext * tc, const StaticInstPtr &inst)
     {
         if (FullSystem) {
+            /* Invalidate any matching TLB entries before handling the page fault */
+            tc->getITBPtr()->demapPage(addr, 0);
+            tc->getDTBPtr()->demapPage(addr, 0);
             HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
             X86FaultBase::invoke(tc);
             /*

diff --git a/src/arch/x86/faults.hh b/src/arch/x86/faults.hh
index f8715ded20386adf2041941f20afb910aacb8608..6eabd53fa652f6e16e02bd6cfd25ee12d965cf23 100644 (file)
--- a/src/arch/x86/faults.hh
+++ b/src/arch/x86/faults.hh
@@ -42,7 +42,7 @@
 
 #include <string>
 
-#include "arch/generic/tlb.hh"
+#include "arch/x86/tlb.hh"
 #include "base/bitunion.hh"
 #include "base/misc.hh"
 #include "sim/faults.hh"