(no commit message)

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index 087d05e6c5294f40e909b287a1568318ceb9e624..197253748738266e374c3e13b3cf37865f111acd 100644 (file)
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -11,9 +11,9 @@ Use of setvl results in changes to the MVL, VL and STATE SPRs. see [[sv/sprs]]
 # Format
 
 | 0.5|6.10|11.15|16.20| 21..24..25  | 26...30 |31|  name   |
-|----|----|-----|-----|-------------|---------|--|---------|
+| -- | -- | --- | --- | ----------- | ------- |--| ------- |
 | 19 | RT | RA  |     | XO[0:4]     | XO[5:9] |Rc| XL-Form |
-| 19 | RT | RA  |imm  | i //  vs ms | NNNNN   |Rc| setvl   |
+| 19 | RT | RA  | imm | i //  vs ms | NNNNN   |Rc| setvl   |
 
 Note that imm spans 7 bits (16 to 22), and that bit 22 is reserved and must be zero.  Setting bit 22 causes an illegal exception.