+2016-10-06  Claudiu Zissulescu  <claziss@synopsys.com>
+
+       * testsuite/gas/arc/leave_enter.d: New file.
+       * testsuite/gas/arc/leave_enter.s: Likewise.
+       * testsuite/gas/arc/regnames.d: Likewise.
+       * testsuite/gas/arc/regnames.s: Likewise.
+       * config/tc-arc.c (arc_parse_name): Don't match reg names against
+       confirmed symbol names.
+
 2016-10-06  Alan Modra  <amodra@gmail.com>
 
        * app.c (do_scrub_chars): Move fall through comment.
 
   if (!assembling_insn)
     return FALSE;
 
-  /* Handle only registers and address types.  */
-  if (e->X_op != O_absent)
+  if (e->X_op == O_symbol)
     return FALSE;
 
   sym = hash_find (arc_reg_hash, name);
 
--- /dev/null
+#objdump: -dr
+
+.*: +file format .*arc.*
+
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.text>:
+   0:  c0c2                    leave_s \[r13-r13\]
+   2:  c4dc                    leave_s \[r13-gp,pcl\]
+   4:  c1dc                    leave_s \[r13-gp,fp\]
+   6:  c2dc                    leave_s \[r13-gp,blink\]
+   8:  c3dc                    leave_s \[r13-gp,fp,blink\]
+   a:  c5dc                    leave_s \[r13-gp,fp,pcl\]
+   c:  c6dc                    leave_s \[r13-gp,blink,pcl\]
+   e:  c7dc                    leave_s \[r13-gp,fp,blink,pcl\]
+  10:  1100 0000               ld      r0,\[r1\]
+  14:  c0e2                    enter_s \[r13-r13\]
+  16:  c1fc                    enter_s \[r13-gp,fp\]
+  18:  c2fc                    enter_s \[r13-gp,blink\]
+  1a:  c3fc                    enter_s \[r13-gp,fp,blink\]
 
--- /dev/null
+       .cpu HS
+       leave_s {r13-r13}
+       leave_s {r13-r26,pcl}
+       leave_s {r13-r26,fp}
+       leave_s {r13-r26,blink}
+       leave_s {r13-r26,fp,blink}
+       leave_s {r13-r26,fp,pcl}
+       leave_s {r13-r26,blink,pcl}
+       leave_s {r13-r26,fp,blink,pcl}
+
+       ld      r0,[r1]
+
+       enter_s {r13-r13}
+       enter_s {r13-r26,fp}
+       enter_s {r13-r26,blink}
+       enter_s {r13-r26,fp,blink}
 
--- /dev/null
+#objdump: -dr
+
+.*: +file format .*arc.*
+
+
+Disassembly of section .text:
+
+[0-9a-f]+ <r0>:
+   0:  200a 0f80 0000 0014     mov     r0,0x14
+   8:  2000 0f80 0000 0000     add     r0,r0,0
+                       c: R_ARC_32_ME  gp
+  10:  1a00 3080               st      r2,\[gp\]
+                       10: R_ARC_SDA_LDST      .text\+0x14
 
--- /dev/null
+;;; Check if assembler can discriminate between labels having the same
+;;; name as a register
+
+r0:
+       mov     r0,@r1-@r0
+       add     r0,r0,@gp
+       st      r2,[gp,@r1@sda]
+r1: