log("passes in the following order:\n");
log("\n");
log(" opt_const [-mux_undef] [-mux_bool] [-undriven] [-fine] [-full] [-keepdc]\n");
- log(" opt_share -nomux\n");
+ log(" opt_share [-share_all] -nomux\n");
log("\n");
log(" do\n");
log(" opt_muxtree\n");
log(" opt_reduce [-fine] [-full]\n");
- log(" opt_share\n");
+ log(" opt_share [-share_all]\n");
log(" opt_rmdff\n");
log(" opt_clean [-purge]\n");
log(" opt_const [-mux_undef] [-mux_bool] [-undriven] [-fine] [-full] [-keepdc]\n");
log("\n");
log(" do\n");
log(" opt_const [-mux_undef] [-mux_bool] [-undriven] [-fine] [-full] [-keepdc]\n");
- log(" opt_share\n");
+ log(" opt_share [-share_all]\n");
log(" opt_rmdff\n");
log(" opt_clean [-purge]\n");
log(" while <changed design in opt_rmdff>\n");
std::string opt_clean_args;
std::string opt_const_args;
std::string opt_reduce_args;
+ std::string opt_share_args;
bool fast_mode = false;
log_header("Executing OPT pass (performing simple optimizations).\n");
opt_const_args += " -keepdc";
continue;
}
+ if (args[argidx] == "-share_all") {
+ opt_share_args += " -share_all";
+ continue;
+ }
if (args[argidx] == "-fast") {
fast_mode = true;
continue;
{
while (1) {
Pass::call(design, "opt_const" + opt_const_args);
- Pass::call(design, "opt_share");
+ Pass::call(design, "opt_share" + opt_share_args);
design->scratchpad_unset("opt.did_something");
Pass::call(design, "opt_rmdff");
if (design->scratchpad_get_bool("opt.did_something") == false)
else
{
Pass::call(design, "opt_const" + opt_const_args);
- Pass::call(design, "opt_share -nomux");
+ Pass::call(design, "opt_share -nomux" + opt_share_args);
while (1) {
design->scratchpad_unset("opt.did_something");
Pass::call(design, "opt_muxtree");
Pass::call(design, "opt_reduce" + opt_reduce_args);
- Pass::call(design, "opt_share");
+ Pass::call(design, "opt_share" + opt_share_args);
Pass::call(design, "opt_rmdff");
Pass::call(design, "opt_clean" + opt_clean_args);
Pass::call(design, "opt_const" + opt_const_args);
RTLIL::Module *module;
SigMap assign_map;
SigMap dff_init_map;
+ bool mode_share_all;
CellTypes ct;
int total_count;
}
for (auto &it : *conn) {
- if (ct.cell_output(cell->type, it.first))
+ if (cell->output(it.first))
continue;
RTLIL::SigSpec sig = it.second;
assign_map.apply(sig);
dict<RTLIL::IdString, RTLIL::SigSpec> conn2 = cell2->connections();
for (auto &it : conn1) {
- if (ct.cell_output(cell1->type, it.first))
+ if (cell1->output(it.first))
it.second = RTLIL::SigSpec();
else
assign_map.apply(it.second);
}
for (auto &it : conn2) {
- if (ct.cell_output(cell2->type, it.first))
+ if (cell2->output(it.first))
it.second = RTLIL::SigSpec();
else
assign_map.apply(it.second);
if (cell1->type != cell2->type)
return cell1->type < cell2->type;
- if (!ct.cell_known(cell1->type))
+ if ((!mode_share_all && !ct.cell_known(cell1->type)) || !cell1->known())
return cell1 < cell2;
if (cell1->has_keep_attr() || cell2->has_keep_attr())
}
};
- OptShareWorker(RTLIL::Design *design, RTLIL::Module *module, bool mode_nomux) :
- design(design), module(module), assign_map(module)
+ OptShareWorker(RTLIL::Design *design, RTLIL::Module *module, bool mode_nomux, bool mode_share_all) :
+ design(design), module(module), assign_map(module), mode_share_all(mode_share_all)
{
total_count = 0;
ct.setup_internals();
std::vector<RTLIL::Cell*> cells;
cells.reserve(module->cells_.size());
for (auto &it : module->cells_) {
- if (ct.cell_known(it.second->type) && design->selected(module, it.second))
+ if (!design->selected(module, it.second))
+ continue;
+ if (ct.cell_known(it.second->type) || (mode_share_all && it.second->known()))
cells.push_back(it.second);
}
did_something = true;
log(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), sharemap[cell]->name.c_str());
for (auto &it : cell->connections()) {
- if (ct.cell_output(cell->type, it.first)) {
+ if (cell->output(it.first)) {
RTLIL::SigSpec other_sig = sharemap[cell]->getPort(it.first);
log(" Redirecting output %s: %s = %s\n", it.first.c_str(),
log_signal(it.second), log_signal(other_sig));
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
- log(" opt_share [-nomux] [selection]\n");
+ log(" opt_share [options] [selection]\n");
log("\n");
log("This pass identifies cells with identical type and input signals. Such cells\n");
log("are then merged to one cell.\n");
log(" -nomux\n");
log(" Do not merge MUX cells.\n");
log("\n");
+ log(" -share_all\n");
+ log(" Operate on all cell types, not just built-in types.\n");
+ log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing OPT_SHARE pass (detect identical cells).\n");
bool mode_nomux = false;
+ bool mode_share_all = false;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
mode_nomux = true;
continue;
}
+ if (arg == "-share_all") {
+ mode_share_all = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
int total_count = 0;
for (auto module : design->selected_modules()) {
- OptShareWorker worker(design, module, mode_nomux);
+ OptShareWorker worker(design, module, mode_nomux, mode_share_all);
total_count += worker.total_count;
}