* `sv.instruction` where any register marked as Vectorised will be
REMAPPED.
+The following illustrative example multiplies a 3x4 and a 5x3
+matrix to create
+a 5x4 result:
+
+ svshape 5, 4, 3, 0, 0
+ svremap 31, 1, 2, 3, 0, 0, 0, 0
+ sv.fmadds 0.v, 8.v, 16.v, 0.v
+
+The example may be executed as a unit test and demo,
+[here](https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_caller_svp64_matrix.py;h=c15479db9a36055166b6b023c7495f9ca3637333;hb=a17a252e474d5d5bf34026c25a19682e3f2015c3#l94)
+
# REMAP SPR
| 0 | 2 | 4 | 6 | 8 | 10.14 | 15..23 |