(no commit message)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 3ef9c84f7095d65a6c9585b3dc376fc410eaa33b..4d15dee4143ec0cd2ff273c35dfd274393d2e192 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -742,10 +742,9 @@ much easier for the main CPU to take over in the event that PEs are
 currently occupied.  Plus, the twin lessons that inventing ISAs, even
 a small one, is hard (mostly in compiler writing) and how complex
 GPU Task Scheduling is, are being heard loud and clear.
-Put another way:
 
-* if the PEs run a foriegn ISA, then the Basic Blocks embedded inside
-  the ZOLC Loops must be in that ISA **OR**
+Put another way: if the PEs run a foriegn ISA, then the Basic Blocks embedded inside the ZOLC Loops must be in that ISA and therefore:
+
 * In order that the main CPU can execute the same sequence if necessary,
   the CPU must support dual ISAs: Power and PE **OR**
 * There must be a JIT binary-translator which either turns PE code