verilog: fix leaking ASTNodes

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 500288de01f5eb0e13d37d5fc87966f09e4f57eb..8ef681069bf97525113afaed4c6aec494a4b8532 100644 (file)
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -2303,6 +2303,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
                        if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
                                log_file_error(filename, location.first_line, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
                        result_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
+                       delete left_at_zero_ast;
+                       delete right_at_zero_ast;
                }
 
                bool use_case_method = false;
@@ -3534,6 +3536,8 @@ skip_dynamic_range_lvalue_expansion:;
                                        // convert purely constant arguments into localparams
                                        if (child->is_input && child->type == AST_WIRE && arg->type == AST_CONSTANT && node_contains_assignment_to(decl, child)) {
                                                wire->type = AST_LOCALPARAM;
+                                               if (wire->attributes.count(ID::nosync))
+                                                       delete wire->attributes.at(ID::nosync);
                                                wire->attributes.erase(ID::nosync);
                                                wire->children.insert(wire->children.begin(), arg->clone());
                                                // args without a range implicitly have width 1
@@ -3557,6 +3561,7 @@ skip_dynamic_range_lvalue_expansion:;
                                                }
                                                // updates the sizing
                                                while (wire->simplify(true, false, false, 1, -1, false, false)) { }
+                                               delete arg;
                                                continue;
                                        }
                                        AstNode *wire_id = new AstNode(AST_IDENTIFIER);

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 3f4bf5bfd9387330f462aabe6848a42cd239f2ae..4e601b51d35c7062fd63a87df5c3a84f25cbde59 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -503,18 +503,19 @@ optional_comma:
 module_arg_opt_assignment:
        '=' expr {
                if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
-                       AstNode *wire = new AstNode(AST_IDENTIFIER);
-                       wire->str = ast_stack.back()->children.back()->str;
                        if (ast_stack.back()->children.back()->is_input) {
                                AstNode *n = ast_stack.back()->children.back();
                                if (n->attributes.count(ID::defaultvalue))
                                        delete n->attributes.at(ID::defaultvalue);
                                n->attributes[ID::defaultvalue] = $2;
-                       } else
-                       if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic)
-                               ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2))));
-                       else
-                               ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2));
+                       } else {
+                               AstNode *wire = new AstNode(AST_IDENTIFIER);
+                               wire->str = ast_stack.back()->children.back()->str;
+                               if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic)
+                                       ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2))));
+                               else
+                                       ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2));
+                       }
                } else
                        frontend_verilog_yyerror("SystemVerilog interface in module port list cannot have a default value.");
        } |
@@ -1158,6 +1159,8 @@ specify_item:
                cell->children.back()->str = "\\DST";
 
                delete $1;
+               delete limit;
+               delete limit2;
        };
 
 specify_opt_triple: