------01000,ALU,OP_MADDSUBRS,RT,CONST_SH,RB,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,maddsubrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
```
+
+# [DRAFT] Floating Twin Multiply-Add DCT [Single]
+
+DCT-Form
+
+```
+ |0 |6 |11 |16 |21 |26 |31 |
+ | PO | FRT | FRA | FRB | // | XO |Rc |
+```
+
+* fdmadds FRT,FRA,FRB (Rc=0)
+* fdmadds. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+```
+ FRS <- FPADD32(FRT, FRB)
+ sub <- FPSUB32(FRT, FRB)
+ FRT <- FPMUL32(FRA, sub)
+```
+
+Special Registers Altered:
+
+```
+ FPRF FR FI
+ FX OX UX XX
+ VXSNAN VXISI VXIMZ
+ CR1 (if Rc=1)
+```