RISC-V: Add 'Zmmul' extension in assembler.

Three-part patch set from Tsukasa OI to support zmmul in assembler.

The 'Zmmul' is a RISC-V extension consisting of only multiply instructions
(a subset of 'M' which has multiply and divide instructions).

bfd/
	* elfxx-riscv.c (riscv_implicit_subsets): Add 'Zmmul' implied by 'M'.
	(riscv_supported_std_z_ext): Add 'Zmmul' extension.
	(riscv_multi_subset_supports): Add handling for new instruction class.
gas/
	* testsuite/gas/riscv/attribute-09.d: Updated implicit 'Zmmul' by 'M'.
	* testsuite/gas/riscv/option-arch-02.d: Likewise.
	* testsuite/gas/riscv/m-ext.s: New test.
	* testsuite/gas/riscv/m-ext-32.d: New test (RV32).
	* testsuite/gas/riscv/m-ext-64.d: New test (RV64).
	* testsuite/gas/riscv/zmmul-32.d: New expected output.
	* testsuite/gas/riscv/zmmul-64.d: Likewise.
	* testsuite/gas/riscv/m-ext-fail-xlen-32.d: New test (failure
	by using RV64-only instructions in RV32).
	* testsuite/gas/riscv/m-ext-fail-xlen-32.l: Likewise.
	* testsuite/gas/riscv/m-ext-fail-zmmul-32.d: New failure test
	(RV32 + Zmmul but with no M).
	* testsuite/gas/riscv/m-ext-fail-zmmul-32.l: Likewise.
	* testsuite/gas/riscv/m-ext-fail-zmmul-64.d: New failure test
	(RV64 + Zmmul but with no M).
	* testsuite/gas/riscv/m-ext-fail-zmmul-64.l: Likewise.
	* testsuite/gas/riscv/m-ext-fail-noarch-64.d: New failure test
	(no Zmmul or M).
	* testsuite/gas/riscv/m-ext-fail-noarch-64.l: Likewise.
include/
	* opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZMMUL.
ld/
	* testsuite/ld-riscv-elf/attr-merge-arch-01.d: We don't care zmmul in
	these testcases, so just replaced m by a.
	* testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-01b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-user-ext-01.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p0.s: Renamed.
	* testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p1.s: Renamed.
opcodes/
	* riscv-opc.c (riscv_opcodes): Updated multiply instructions to zmmul.

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index c9636bcbdc891cf0cab9f3fb3ba5e5ed893c6502..8cb3c8d49302f6799d502380d9386af4038bd523 100644 (file)
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1039,6 +1039,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"e", "i",           check_implicit_always},
   {"i", "zicsr",       check_implicit_for_i},
   {"i", "zifencei",    check_implicit_for_i},
+  {"m", "zmmul",       check_implicit_always},
   {"g", "i",           check_implicit_always},
   {"g", "m",           check_implicit_always},
   {"g", "a",           check_implicit_always},
@@ -1160,6 +1161,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zifencei",         ISA_SPEC_CLASS_20191213,        2, 0,  0 },
   {"zifencei",         ISA_SPEC_CLASS_20190608,        2, 0,  0 },
   {"zihintpause",      ISA_SPEC_CLASS_DRAFT,           2, 0,  0 },
+  {"zmmul",            ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zfh",              ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zfhmin",           ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zfinx",            ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
@@ -2287,6 +2289,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zihintpause");
     case INSN_CLASS_M:
       return riscv_subset_supports (rps, "m");
+    case INSN_CLASS_ZMMUL:
+      return riscv_subset_supports (rps, "zmmul");
     case INSN_CLASS_A:
       return riscv_subset_supports (rps, "a");
     case INSN_CLASS_F:
@@ -2402,6 +2406,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "zihintpause";
     case INSN_CLASS_M:
       return "m";
+    case INSN_CLASS_ZMMUL:
+      return _ ("m' or `zmmul");
     case INSN_CLASS_A:
       return "a";
     case INSN_CLASS_F:

diff --git a/gas/testsuite/gas/riscv/attribute-09.d b/gas/testsuite/gas/riscv/attribute-09.d
index fc87f82c5544fc6063545b622c7e212ebdf21499..c92dc970eea2d3ee66ce38657de047b078335b45 100644 (file)
--- a/gas/testsuite/gas/riscv/attribute-09.d
+++ b/gas/testsuite/gas/riscv/attribute-09.d
@@ -3,4 +3,4 @@
 #source: empty.s
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv32i2p2_m2p0_zicsr2p0"
+  Tag_RISCV_arch: "rv32i2p2_m2p0_zicsr2p0_zmmul1p0"

diff --git a/gas/testsuite/gas/riscv/m-ext-32.d b/gas/testsuite/gas/riscv/m-ext-32.d
new file mode 100644 (file)
index 0000000..fe2ef9a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-32.d
@@ -0,0 +1,18 @@
+#as: -march=rv32im
+#source: m-ext.s
+#objdump: -d
+
+.*:[   ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[      ]+[0-9a-f]+:[   ]+02c58533[     ]+mul[          ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+02c59533[     ]+mulh[         ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+02c5a533[     ]+mulhsu[       ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+02c5b533[     ]+mulhu[        ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+02c5c533[     ]+div[          ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+02c5d533[     ]+divu[         ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+02c5e533[     ]+rem[          ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+02c5f533[     ]+remu[         ]+a0,a1,a2

diff --git a/gas/testsuite/gas/riscv/m-ext-64.d b/gas/testsuite/gas/riscv/m-ext-64.d
new file mode 100644 (file)
index 0000000..05099b1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-64.d
@@ -0,0 +1,23 @@
+#as: -march=rv64im -defsym rv64=1
+#source: m-ext.s
+#objdump: -d
+
+.*:[   ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[      ]+[0-9a-f]+:[   ]+02c58533[     ]+mul[          ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+02c59533[     ]+mulh[         ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+02c5a533[     ]+mulhsu[       ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+02c5b533[     ]+mulhu[        ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+02c5c533[     ]+div[          ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+02c5d533[     ]+divu[         ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+02c5e533[     ]+rem[          ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+02c5f533[     ]+remu[         ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+02c5853b[     ]+mulw[         ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+02c5c53b[     ]+divw[         ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+02c5d53b[     ]+divuw[        ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+02c5e53b[     ]+remw[         ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+02c5f53b[     ]+remuw[        ]+a0,a1,a2

diff --git a/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d b/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d
new file mode 100644 (file)
index 0000000..3c4fc9a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d
@@ -0,0 +1,4 @@
+#as: -march=rv64i -defsym rv64=1
+#source: m-ext.s
+#objdump: -d
+#error_output: m-ext-fail-noarch-64.l

diff --git a/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l b/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l
new file mode 100644 (file)
index 0000000..db9c8fb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l
@@ -0,0 +1,14 @@
+.*Assembler messages:
+.*: Error: unrecognized opcode `mul a0,a1,a2', extension `m' or `zmmul' required
+.*: Error: unrecognized opcode `mulh a0,a1,a2', extension `m' or `zmmul' required
+.*: Error: unrecognized opcode `mulhsu a0,a1,a2', extension `m' or `zmmul' required
+.*: Error: unrecognized opcode `mulhu a0,a1,a2', extension `m' or `zmmul' required
+.*: Error: unrecognized opcode `div a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `divu a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `rem a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `remu a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `mulw a0,a1,a2', extension `m' or `zmmul' required
+.*: Error: unrecognized opcode `divw a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `divuw a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `remw a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `remuw a0,a1,a2', extension `m' required

diff --git a/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
new file mode 100644 (file)
index 0000000..54f8b82
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
@@ -0,0 +1,4 @@
+#as: -march=rv32im -defsym rv64=1
+#source: m-ext.s
+#objdump: -d
+#error_output: m-ext-fail-xlen-32.l

diff --git a/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
new file mode 100644 (file)
index 0000000..d65ca49
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
@@ -0,0 +1,6 @@
+.*Assembler messages:
+.*: Error: unrecognized opcode `mulw a0,a1,a2'
+.*: Error: unrecognized opcode `divw a0,a1,a2'
+.*: Error: unrecognized opcode `divuw a0,a1,a2'
+.*: Error: unrecognized opcode `remw a0,a1,a2'
+.*: Error: unrecognized opcode `remuw a0,a1,a2'

diff --git a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d
new file mode 100644 (file)
index 0000000..c164fa9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d
@@ -0,0 +1,4 @@
+#as: -march=rv32i_zmmul
+#source: m-ext.s
+#objdump: -d
+#error_output: m-ext-fail-zmmul-32.l

diff --git a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l
new file mode 100644 (file)
index 0000000..0151001
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l
@@ -0,0 +1,5 @@
+.*Assembler messages:
+.*: Error: unrecognized opcode `div a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `divu a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `rem a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `remu a0,a1,a2', extension `m' required

diff --git a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
new file mode 100644 (file)
index 0000000..f736d9c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
@@ -0,0 +1,4 @@
+#as: -march=rv64i_zmmul -defsym rv64=1
+#source: m-ext.s
+#objdump: -d
+#error_output: m-ext-fail-zmmul-64.l

diff --git a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l
new file mode 100644 (file)
index 0000000..7779973
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l
@@ -0,0 +1,9 @@
+.*Assembler messages:
+.*: Error: unrecognized opcode `div a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `divu a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `rem a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `remu a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `divw a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `divuw a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `remw a0,a1,a2', extension `m' required
+.*: Error: unrecognized opcode `remuw a0,a1,a2', extension `m' required

diff --git a/gas/testsuite/gas/riscv/m-ext.s b/gas/testsuite/gas/riscv/m-ext.s
new file mode 100644 (file)
index 0000000..68baf2a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext.s
@@ -0,0 +1,21 @@
+target:
+       mul     a0, a1, a2
+       mulh    a0, a1, a2
+       mulhsu  a0, a1, a2
+       mulhu   a0, a1, a2
+.ifndef zmmul
+       div     a0, a1, a2
+       divu    a0, a1, a2
+       rem     a0, a1, a2
+       remu    a0, a1, a2
+.endif
+
+.ifdef rv64
+       mulw    a0, a1, a2
+.ifndef zmmul
+       divw    a0, a1, a2
+       divuw   a0, a1, a2
+       remw    a0, a1, a2
+       remuw   a0, a1, a2
+.endif
+.endif

diff --git a/gas/testsuite/gas/riscv/option-arch-02.d b/gas/testsuite/gas/riscv/option-arch-02.d
index 9ca013e507ef12175688c0cee82741f7e78882b3..3c27419f9d3687529f6897ce8b956a61b2f6f5f4 100644 (file)
--- a/gas/testsuite/gas/riscv/option-arch-02.d
+++ b/gas/testsuite/gas/riscv/option-arch-02.d
@@ -4,5 +4,5 @@
 
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv64i2p0_m3p0_f2p0_d3p0_c2p0_xvendor32x3p0"
+  Tag_RISCV_arch: "rv64i2p0_m3p0_f2p0_d3p0_c2p0_zmmul1p0_xvendor32x3p0"
 #...

diff --git a/gas/testsuite/gas/riscv/zmmul-32.d b/gas/testsuite/gas/riscv/zmmul-32.d
new file mode 100644 (file)
index 0000000..c9cf56a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zmmul-32.d
@@ -0,0 +1,14 @@
+#as: -march=rv32im -defsym zmmul=1
+#source: m-ext.s
+#objdump: -d
+
+.*:[   ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[      ]+[0-9a-f]+:[   ]+02c58533[     ]+mul[          ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+02c59533[     ]+mulh[         ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+02c5a533[     ]+mulhsu[       ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+02c5b533[     ]+mulhu[        ]+a0,a1,a2

diff --git a/gas/testsuite/gas/riscv/zmmul-64.d b/gas/testsuite/gas/riscv/zmmul-64.d
new file mode 100644 (file)
index 0000000..67ef360
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zmmul-64.d
@@ -0,0 +1,15 @@
+#as: -march=rv64im -defsym zmmul=1 -defsym rv64=1
+#source: m-ext.s
+#objdump: -d
+
+.*:[   ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[      ]+[0-9a-f]+:[   ]+02c58533[     ]+mul[          ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+02c59533[     ]+mulh[         ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+02c5a533[     ]+mulhsu[       ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+02c5b533[     ]+mulhu[        ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+02c5853b[     ]+mulw[         ]+a0,a1,a2

diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index b115e338a05b9f0b2ff0825a68477cfe30a79817..f1dabeaab8e4f929e9121fcb9e51dd4e11cdbfbb 100644 (file)
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -367,6 +367,7 @@ enum riscv_insn_class
   INSN_CLASS_ZICSR,
   INSN_CLASS_ZIFENCEI,
   INSN_CLASS_ZIHINTPAUSE,
+  INSN_CLASS_ZMMUL,
   INSN_CLASS_F_OR_ZFINX,
   INSN_CLASS_D_OR_ZDINX,
   INSN_CLASS_Q_OR_ZQINX,

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
index a4b0322a3d926e50410cb16fd9f3f5e19bc05dd6..de87f6003877ca22ffb6fc5d1a83cedea8c9522e 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
@@ -6,4 +6,4 @@
 
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv32i2p1_m2p0"
+  Tag_RISCV_arch: "rv32i2p1_a2p0"

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s
index ea097f99b04263fc4af76d5f86812bf3737d0a1a..4593241c02498637ffe89116eab60b3c7a853ec0 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s
@@ -1 +1 @@
-       .attribute arch, "rv32i2p1_m2p0"
+       .attribute arch, "rv32i2p1_a2p0"

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s
index ea097f99b04263fc4af76d5f86812bf3737d0a1a..4593241c02498637ffe89116eab60b3c7a853ec0 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s
@@ -1 +1 @@
-       .attribute arch, "rv32i2p1_m2p0"
+       .attribute arch, "rv32i2p1_a2p0"

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
index 852fd55ae08270a399e7505a5a53384b43a89b09..381ef850d974a7a390e25a323c66062662e8966e 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
@@ -6,4 +6,4 @@
 
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv32i2p1_m2p0"
+  Tag_RISCV_arch: "rv32i2p1_a2p0"

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s
index ea097f99b04263fc4af76d5f86812bf3737d0a1a..4593241c02498637ffe89116eab60b3c7a853ec0 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s
@@ -1 +1 @@
-       .attribute arch, "rv32i2p1_m2p0"
+       .attribute arch, "rv32i2p1_a2p0"

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
index c1cf8081dc7ee811bb58f790d5ef328bf94ff68e..6419fe89791259ef06188bb9c61fe2deabe04a09 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
@@ -6,4 +6,4 @@
 
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv32i2p1_m2p0_xbar2p0_xfoo2p0"
+  Tag_RISCV_arch: "rv32i2p1_a2p0_xbar2p0_xfoo2p0"

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s
index 3a9fb97ac4eb79fe109e2eb7c694302043cdb99a..603b5d678ffd569555391c168077e84eafa27635 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s
@@ -1 +1 @@
-       .attribute arch, "rv32i2p1_m2p0_xfoo2p0"
+       .attribute arch, "rv32i2p1_a2p0_xfoo2p0"

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-01.d
index d15bcdcab1bcd6a2a54fa8bf85e3f2fdbcba167c..f4012dcf90d8c88204984bc90b5adbcd01569229 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-01.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-01.d
@@ -1,9 +1,9 @@
-#source: attr-merge-user-ext-rv32i2p1_m2p0.s
-#source: attr-merge-user-ext-rv32i2p1_m2p1.s
+#source: attr-merge-user-ext-rv32i2p1_a2p0.s
+#source: attr-merge-user-ext-rv32i2p1_a2p1.s
 #as:
 #ld: -r -m[riscv_choose_ilp32_emul]
 #readelf: -A
 
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv32i2p1_m2p1"
+  Tag_RISCV_arch: "rv32i2p1_a2p1"

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p0.s b/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p0.s
new file mode 100644 (file)
index 0000000..0d4fba5
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p0.s
@@ -0,0 +1 @@
+.attribute arch, "rv32i2p1_a2p0"

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p1.s b/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p1.s
new file mode 100644 (file)
index 0000000..ded3583
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p1.s
@@ -0,0 +1 @@
+.attribute arch, "rv32i2p1_a2p1"

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_m2p0.s b/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_m2p0.s
deleted file mode 100644 (file)
index a7e0547..0000000
--- a/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_m2p0.s
+++ /dev/null
@@ -1 +0,0 @@
-.attribute arch, "rv32i2p1_m2p0"

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_m2p1.s b/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_m2p1.s
deleted file mode 100644 (file)
index a1b61e3..0000000
--- a/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_m2p1.s
+++ /dev/null
@@ -1 +0,0 @@
-.attribute arch, "rv32i2p1_m2p1"

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 2f9945aa93009bd9dc3e12b1fe2b8976c392163b..79be78eb367f1d4dd7ce1a05116fa9f408ef5867 100644 (file)
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -558,19 +558,19 @@ const struct riscv_opcode riscv_opcodes[] =
 {"amominu.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D|MASK_AQRL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
 
 /* Multiply/Divide instruction subset.  */
-{"mul",        0, INSN_CLASS_M,   "d,s,t",     MATCH_MUL, MASK_MUL, match_opcode, 0 },
-{"mulh",       0, INSN_CLASS_M,   "d,s,t",     MATCH_MULH, MASK_MULH, match_opcode, 0 },
-{"mulhu",      0, INSN_CLASS_M,   "d,s,t",     MATCH_MULHU, MASK_MULHU, match_opcode, 0 },
-{"mulhsu",     0, INSN_CLASS_M,   "d,s,t",     MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 },
-{"div",        0, INSN_CLASS_M,   "d,s,t",     MATCH_DIV, MASK_DIV, match_opcode, 0 },
-{"divu",       0, INSN_CLASS_M,   "d,s,t",     MATCH_DIVU, MASK_DIVU, match_opcode, 0 },
-{"rem",        0, INSN_CLASS_M,   "d,s,t",     MATCH_REM, MASK_REM, match_opcode, 0 },
-{"remu",       0, INSN_CLASS_M,   "d,s,t",     MATCH_REMU, MASK_REMU, match_opcode, 0 },
-{"mulw",      64, INSN_CLASS_M,   "d,s,t",     MATCH_MULW, MASK_MULW, match_opcode, 0 },
-{"divw",      64, INSN_CLASS_M,   "d,s,t",     MATCH_DIVW, MASK_DIVW, match_opcode, 0 },
-{"divuw",     64, INSN_CLASS_M,   "d,s,t",     MATCH_DIVUW, MASK_DIVUW, match_opcode, 0 },
-{"remw",      64, INSN_CLASS_M,   "d,s,t",     MATCH_REMW, MASK_REMW, match_opcode, 0 },
-{"remuw",     64, INSN_CLASS_M,   "d,s,t",     MATCH_REMUW, MASK_REMUW, match_opcode, 0 },
+{"mul",        0, INSN_CLASS_ZMMUL, "d,s,t",     MATCH_MUL, MASK_MUL, match_opcode, 0 },
+{"mulh",       0, INSN_CLASS_ZMMUL, "d,s,t",     MATCH_MULH, MASK_MULH, match_opcode, 0 },
+{"mulhu",      0, INSN_CLASS_ZMMUL, "d,s,t",     MATCH_MULHU, MASK_MULHU, match_opcode, 0 },
+{"mulhsu",     0, INSN_CLASS_ZMMUL, "d,s,t",     MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 },
+{"div",        0, INSN_CLASS_M,     "d,s,t",     MATCH_DIV, MASK_DIV, match_opcode, 0 },
+{"divu",       0, INSN_CLASS_M,     "d,s,t",     MATCH_DIVU, MASK_DIVU, match_opcode, 0 },
+{"rem",        0, INSN_CLASS_M,     "d,s,t",     MATCH_REM, MASK_REM, match_opcode, 0 },
+{"remu",       0, INSN_CLASS_M,     "d,s,t",     MATCH_REMU, MASK_REMU, match_opcode, 0 },
+{"mulw",      64, INSN_CLASS_ZMMUL, "d,s,t",     MATCH_MULW, MASK_MULW, match_opcode, 0 },
+{"divw",      64, INSN_CLASS_M,     "d,s,t",     MATCH_DIVW, MASK_DIVW, match_opcode, 0 },
+{"divuw",     64, INSN_CLASS_M,     "d,s,t",     MATCH_DIVUW, MASK_DIVUW, match_opcode, 0 },
+{"remw",      64, INSN_CLASS_M,     "d,s,t",     MATCH_REMW, MASK_REMW, match_opcode, 0 },
+{"remuw",     64, INSN_CLASS_M,     "d,s,t",     MATCH_REMUW, MASK_REMUW, match_opcode, 0 },
 
 /* Half-precision floating-point instruction subset.  */
 {"flh",        0, INSN_CLASS_ZFHMIN,   "D,o(s)",    MATCH_FLH, MASK_FLH, match_opcode, INSN_DREF|INSN_2_BYTE },