move setb to discussion for ls015, add page-breaks

diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn
index 18aa562fb34df188ce237f610fc2806d60fa2165..68a8e930c2a9d2b00eba5633cc8cca4ed2201468 100644 (file)
--- a/openpower/sv/cr_int_predication.mdwn
+++ b/openpower/sv/cr_int_predication.mdwn
@@ -1,5 +1,3 @@
-[[!tag standards]]
-
 # New instructions for CR/INT predication
 
 **DRAFT STATUS**
@@ -11,6 +9,7 @@ See:
 * <https://bugs.libre-soc.org/show_bug.cgi?id=527>
 * <https://bugs.libre-soc.org/show_bug.cgi?id=569>
 * <https://bugs.libre-soc.org/show_bug.cgi?id=558#c47>
+* [[discussion]]
 
 Rationale:
 
@@ -78,6 +77,10 @@ Useful side-effects:
 Please see [[svp64/appendix]] regarding CR bit ordering and for
 the definition of `CR{n}`
 
+----------
+
+\newpage{}
+
 # Instruction form and pseudocode
 
 **DRAFT** Instruction format (use of MAJOR 19 not approved by
@@ -254,6 +257,10 @@ on the `BT` CR bit. When M=0 it is a more normal Write.
     mtcrset BF, fmsk  mtcrweird BF, r0, 1, fmsk,0b0000
     mtcrclr BF, fmsk  mtcrweird BF, r0, 1, fmsk,0b1111
 
+----------
+
+\newpage{}
+
 # Vectorised versions involving GPRs
 
 The name "weird" refers to a minor violation of SV rules when it comes
@@ -381,16 +388,6 @@ results are set to zero.
             idx, boff = 0, i
         iregs[RT+idx][60-boff*4:63-boff*4] = result
 
-# v3.1 setbc instructions
-
-There are additional setb conditional instructions in v3.1 (p129)
-
-    RT = (CR[BI] == 1) ? 1 : 0
-
-which also negate that, and also return -1 / 0.  these are similar to
-crweird but not the same purpose.  most notable is that crweird acts on
-CR fields rather than the entire 32 bit CR.
-
 # Predication Examples
 
 Take the following example:
@@ -427,3 +424,9 @@ By using twin predication, zeroing, and inversion (sm=~r3, dm=r10) for
 example, it becomes possible to combine two Integers together in order
 to set bits in CR Fields.  Likewise there are dozens of ways that CR
 Predicates can be used, on the same sv.mtcrweird instruction.
+
+
+[[!tag standards]]
+----------
+
+\newpage{}

diff --git a/openpower/sv/cr_int_predication/discussion.mdwn b/openpower/sv/cr_int_predication/discussion.mdwn
new file mode 100644 (file)
index 0000000..979897a
--- /dev/null
+++ b/openpower/sv/cr_int_predication/discussion.mdwn
@@ -0,0 +1,11 @@
+# v3.1 setbc instructions
+
+There are additional setb conditional instructions in v3.1 (p129)
+
+    RT = (CR[BI] == 1) ? 1 : 0
+
+which also negate that, and also return -1 / 0.  these are similar to
+crweird but not the same purpose.  most notable is that crweird acts on
+CR fields rather than the entire 32 bit CR.
+
+