immed in same 6 bits
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 29 Jun 2019 07:45:15 +0000 (08:45 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 29 Jun 2019 07:45:15 +0000 (08:45 +0100)
simple_v_extension/vblock_format_table.mdwn

index d381ede9fd57053164d3c1a9fdc44800bf01f508..97b81209297a68e98b15763311367fb9830df8bc 100644 (file)
@@ -14,10 +14,10 @@ of the RISC-V ISA, is as follows:
 The VL/MAXVL/SubVL Block format:
 
 [[!table  data="""
-31:30 | 29:28 | 27:22  | 21:19    | 18:16    | comment              |
-0b00  | SubVL | VLdest | imm[5:0]           || VL set from imm      |
-0b01  | SubVL | MVLimm | rs1[2:0] | rd[2:0]  | RVC reg format       |
-0b10  | SubVL | VLdest | imm[5:0]           || VL & MVL set from imm|
-0b11  | rsvd  | rsvd   | rsvd     | rsvd     | reserved, all 0s     |
+31:30 | 29:28 | 27:22  | 21 | 20:19   | 18:16    | comment              |
+0b00  | SubVL |imm[5:0]|rsvd| rd[4:0]           || VL set from imm      |
+0b01  | SubVL |imm[5:0]| rs1[2:0]    || rd[2:0]  | RVC reg format       |
+0b10  | SubVL |imm[5:0]|rsvd|   rd[4:0]     || VL & MVL set from imm|
+0b11  | rsvd  | rsvd   |rsvd|      rsvd     || reserved, all 0s     |
 """]]