(no commit message)

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index bfa4bac8cda8aad7a679708dc74142f89f194b7f..baa34f3192ad2a97df0f97ccfaeceecb57103ca4 100644 (file)
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -21,7 +21,7 @@ explicit Vector opcode exists in SV, at all**.
 
 Fundamental design principles:
 
-* Simplicity of introduction and implementation on the existing OpenPOWER ISA
+* Simplicity of introduction and implementation on the existing Power ISA
 * Effectively a hardware for-loop, pausing PC, issuing multiple scalar
   operations
 * Preserving the underlying scalar execution dependencies as if the
@@ -29,7 +29,7 @@ Fundamental design principles:
   (termed "preserving Program Order")
 * Augments ("tags") existing instructions, providing Vectorisation
   "context" rather than adding new ones.
-* Does not modify or deviate from the underlying scalar OpenPOWER ISA
+* Does not modify or deviate from the underlying scalar Power ISA
   unless it provides significant performance or other advantage to do so
   in the Vector space (dropping XER.SO for example)
 * Designed for Supercomputing: avoids creating significant sequential
@@ -47,7 +47,7 @@ Advantages of these design principles:
 * More complex HDL can be done by repeating existing scalar ALUs and 
   pipelines as blocks and leveraging existing Multi-Issue Infrastructure
 * As (mostly) a high-level "context" that does not (significantly) deviate
-  from scalar OpenPOWER ISA and, in its purest form being "a for loop around
+  from scalar Power ISA and, in its purest form being "a for loop around
   scalar instructions", it is minimally-disruptive and consequently stands
   a reasonable chance of broad community adoption and acceptance
 * Completely wipes not just SIMD opcode proliferation off the