compat: fix confusing naming for memory port address signal.

diff --git a/nmigen/compat/fhdl/specials.py b/nmigen/compat/fhdl/specials.py
index 0c27c57ff90199213472075351e7c05defe3d49a..5449ba6f8412c8f77488533af2e5ad3ea8e1a967 100644 (file)
--- a/nmigen/compat/fhdl/specials.py
+++ b/nmigen/compat/fhdl/specials.py
@@ -64,6 +64,7 @@ class CompatMemory(NativeMemory):
             we_granularity = None
         assert mode != NO_CHANGE
         rdport = self.read_port(synchronous=not async_read, transparent=mode == WRITE_FIRST)
+        rdport.addr.name = "{}_addr".format(self.name)
         adr = rdport.addr
         dat_r = rdport.data
         if write_capable: