integration/soc/add_uart: add Model/Sim.

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 91d446028a51dbb0a2654fdc191bee4840ebd350..53684fdf74b9546d2c3ce323c09ae9e57d96b038 100644 (file)
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -931,6 +931,13 @@ class LiteXSoC(SoC):
         elif name in ["crossover"]:
             self.submodules.uart = uart.UARTCrossover()
 
+        # Model/Sim
+        elif name in ["model", "sim"]:
+            self.submodules.uart_phy = uart.RS232PHYModel(self.platform.request("serial"))
+            self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy,
+                tx_fifo_depth = fifo_depth,
+                rx_fifo_depth = fifo_depth))
+
         # JTAG Atlantic
         elif name in ["jtag_atlantic"]:
             from litex.soc.cores.jtag import JTAGAtlantic