ARM: Implement numcpus bits in L2CTLR register.

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 676abfa6896892b81381d532f9d3b2ee7cca7303..b504550a1d304372fa6476bfc039bb07de88dc6b 100644 (file)
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -227,6 +227,12 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
         return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
       case MISCREG_FPSCR_EXC:
         return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
+      case MISCREG_L2CTLR:
+        // mostly unimplemented, just set NumCPUs field from sim and return
+        L2CTLR l2ctlr = 0;
+        // b00:1CPU to b11:4CPUs
+        l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
+        return l2ctlr;
     }
     return readMiscRegNoEffect(misc_reg);
 }
@@ -537,6 +543,9 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
             // see all of the registers for the copy.
             updateRegMap(val);
             return;
+          case MISCREG_L2CTLR:
+            warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
+                 miscRegName[misc_reg], uint32_t(val));
         }
     }
     setMiscRegNoEffect(misc_reg, newVal);

diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index fc04ce87dec45b47fd0221cd22b541bf28ceb20e..1fecaa38d65368896da85303fd6312dacf6a1afd 100644 (file)
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -382,7 +382,19 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
                 }
             }
         } else if (opc1 == 1) {
-            return MISCREG_L2LATENCY;
+            switch (crm) {
+              case 0:
+                switch (opc2) {
+                  case 2: // L2CTLR, L2 Control Register
+                    return MISCREG_L2CTLR;
+                  default:
+                    warn("Uknown miscregs: crn:%d crm:%d opc1:%d opc2:%d\n",
+                         crn,crm, opc1,opc2);
+                    break;
+                }
+              default:
+                return MISCREG_L2LATENCY;
+            }
         }
         //Reserved for Branch Predictor, Cache and TCM operations
         break;

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 97ac58e02c5bbce9fb4e8aaf261a460ab3782741..f99748622eb905a37187b156876ee926d94a111b 100644 (file)
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -177,6 +177,7 @@ namespace ArmISA
         MISCREG_LOCKFLAG,
         MISCREG_LOCKADDR,
         MISCREG_ID_PFR1,
+        MISCREG_L2CTLR,
         MISCREG_CP15_UNIMP_START,
         MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
         MISCREG_ID_DFR0,
@@ -238,6 +239,7 @@ namespace ArmISA
         "pmuserenr", "pmintenset", "pmintenclr",
         "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
         "cpsr_mode", "lockflag", "lockaddr", "id_pfr1",
+        "l2ctlr",
          // Unimplemented below
         "tcmtr",
         "id_dfr0", "id_afr0",
@@ -432,6 +434,23 @@ namespace ArmISA
        Bitfield<31,30> or7;
    EndBitUnion(NMRR)
 
+   BitUnion32(L2CTLR)
+      Bitfield<2,0>   sataRAMLatency;
+      Bitfield<4,3>   reserved_4_3;
+      Bitfield<5>     dataRAMSetup;
+      Bitfield<8,6>   tagRAMLatency;
+      Bitfield<9>     tagRAMSetup;
+      Bitfield<11,10> dataRAMSlice;
+      Bitfield<12>    tagRAMSlice;
+      Bitfield<20,13> reserved_20_13;
+      Bitfield<21>    eccandParityEnable;
+      Bitfield<22>    reserved_22;
+      Bitfield<23>    interptCtrlPresent;
+      Bitfield<25,24> numCPUs;
+      Bitfield<30,26> reserved_30_26;
+      Bitfield<31>    l2rstDISABLE_monitor;
+   EndBitUnion(L2CTLR)
+
 };
 
 #endif // __ARCH_ARM_MISCREGS_HH__