Try and fix again
authorEddie Hung <eddie@fpgeh.com>
Fri, 19 Jul 2019 21:40:57 +0000 (14:40 -0700)
committerEddie Hung <eddie@fpgeh.com>
Fri, 19 Jul 2019 21:40:57 +0000 (14:40 -0700)
passes/opt/wreduce.cc

index 908a85d5b5304243ea8e371579c137fe32a8057f..22af0bd8b68893fc03f0666662c7ba1bcd8d700a 100644 (file)
@@ -372,13 +372,12 @@ struct WreduceWorker
 
                        int i;
                        for (i = 0; i < GetSize(sig); i++) {
-                               if (B.at(i, Sx) != S0 && (sub || A.at(i, Sx) != S0))
-                                       break;
-                               if (B[i] == S0)
+                               if (B.at(i, Sx) == S0 && A.at(i, Sx) != Sx)
                                        module->connect(sig[i], A[i]);
-                               else if (A[i] == S0)
+                               else if (!sub && A.at(i, Sx) == S0 && B.at(i, Sx) != Sx)
                                        module->connect(sig[i], B[i]);
-                               else log_abort();
+                               else
+                                       break;
                        }
                        if (i > 0) {
                                cell->setPort("\\A", A.extract(i, -1));