boolean uses_kill; /**< KIL or KILP instruction used? */
boolean uses_fogcoord; /**< fragment shader uses fog coord? */
boolean uses_frontfacing; /**< fragment shader uses front/back-face flag? */
+
+ uint texture_max;
+ uint texture_mask;
};
brw_pipe_blend.c \
brw_pipe_depth.c \
brw_pipe_fb.c \
- brw_pipe_flush.c \
brw_pipe_query.c \
- brw_pipe_shader.c \
- brw_screen_surface.c \
brw_sf.c \
brw_sf_emit.c \
brw_sf_state.c \
brw_state_dump.c \
brw_state_upload.c \
brw_swtnl.c \
- brw_tex.c \
- brw_tex_layout.c \
brw_urb.c \
brw_util.c \
brw_vs.c \
brw_wm_sampler_state.c \
brw_wm_state.c \
brw_wm_surface_state.c \
+ brw_screen_surface.c \
+ brw_screen_texture.c \
brw_bo.c \
brw_batchbuffer.c \
+ brw_pipe_shader.c \
+ brw_pipe_flush.c \
intel_tex_layout.c
include ../../Makefile.template
}
- if (INTEL_DEBUG & DEBUG_BATCH)
- fprintf(stderr, "%s:%d: Batchbuffer flush with %db used\n", file, line,
+ if (BRW_DEBUG & DEBUG_BATCH)
+ debug_printf("%s:%d: Batchbuffer flush with %db used\n", file, line,
used);
/* Emit a flush if the bufmgr doesn't do it for us. */
if (intel->always_flush_cache || !intel->ttm) {
- *(GLuint *) (batch->ptr) = intel->vtbl.flush_cmd();
+ *(GLuint *) (batch->ptr) = ((CMD_MI_FLUSH << 16) | BRW_FLUSH_STATE_CACHE);
batch->ptr += 4;
used = batch->ptr - batch->map;
}
batch->sws->bo_exec(batch->buf, used, NULL, 0, 0 );
- if (INTEL_DEBUG & DEBUG_BATCH) {
+ if (BRW_DEBUG & DEBUG_BATCH) {
dri_bo_map(batch->buf, GL_FALSE);
intel_decode(batch->buf->virtual, used / 4, batch->buf->offset,
brw->brw_screen->pci_id);
dri_bo_unmap(batch->buf);
}
- if (INTEL_DEBUG & DEBUG_SYNC) {
- fprintf(stderr, "waiting for idle\n");
+ if (BRW_DEBUG & DEBUG_SYNC) {
+ debug_printf("waiting for idle\n");
dri_bo_map(batch->buf, GL_TRUE);
dri_bo_unmap(batch->buf);
}
int ret;
if (batch->ptr - batch->map > batch->buf->size)
- _mesa_printf ("bad relocation ptr %p map %p offset %d size %d\n",
+ debug_printf ("bad relocation ptr %p map %p offset %d size %d\n",
batch->ptr, batch->map, batch->ptr - batch->map, batch->buf->size);
ret = batch->sws->bo_emit_reloc(batch->buf,
#define PIPE_NEW_FRAMEBUFFER_DIMENSIONS 0x10000
#define PIPE_NEW_DEPTH_BUFFER 0x20000
#define PIPE_NEW_COLOR_BUFFERS 0x40000
+#define PIPE_NEW_QUERY 0x80000
+#define PIPE_NEW_SCISSOR 0x100000
#define BRW_NEW_WM_INPUT_DIMENSIONS 0x100
#define BRW_NEW_PSP 0x800
#define BRW_NEW_WM_SURFACES 0x1000
-#define BRW_NEW_FENCE 0x2000
+#define BRW_NEW_xxx 0x2000 /* was FENCE */
#define BRW_NEW_INDICES 0x4000
#define BRW_NEW_VERTICES 0x8000
/**
struct brw_cache {
struct brw_context *brw;
+ struct brw_winsys_screen *sws;
struct brw_cache_item **items;
GLuint size, n_items;
GLuint key_size[BRW_MAX_CACHE]; /* for fixed-size keys */
GLuint aux_size[BRW_MAX_CACHE];
char *name[BRW_MAX_CACHE];
+
/* Record of the last BOs chosen for each cache_id. Used to set
* brw->state.dirty.cache when a new cache item is chosen.
int last_index;
/* Total count of pixels from previous BOs */
- unsigned int count;
+ uint64_t result;
};
const struct brw_rasterizer_state *rast;
const struct brw_depth_stencil_state *zstencil;
+ const struct pipe_texture *texture[PIPE_MAX_SAMPLERS];
+ const struct pipe_sampler *sampler[PIPE_MAX_SAMPLERS];
+ unsigned num_textures;
+ unsigned num_samplers;
+
+
struct pipe_vertex_element vertex_element[PIPE_MAX_ATTRIBS];
struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
unsigned num_vertex_elements;
unsigned num_vertex_buffers;
+ struct pipe_scissor_state scissor;
struct pipe_framebuffer_state fb;
struct pipe_viewport_state vp;
struct pipe_clip_state ucp;
struct brw_blend_constant_color bcc;
struct brw_polygon_stipple bps;
+
+
/**
* Index buffer for this draw_prims call.
*
struct brw_winsys_buffer *bo;
int index;
GLboolean active;
+ int stats_wm;
} query;
struct {
GLboolean need_stall = 0;
if (writemask == 0) {
- /*_mesa_printf("%s: zero writemask??\n", __FUNCTION__); */
+ /*debug_printf("%s: zero writemask??\n", __FUNCTION__); */
return;
}
if (newmask != writemask) {
need_stall = 1;
- /* _mesa_printf("need stall %x %x\n", newmask , writemask); */
+ /* debug_printf("need stall %x %x\n", newmask , writemask); */
}
else {
struct brw_reg m1 = brw_message_reg(msg_reg_nr);
void brw_pipe_framebuffer_init( struct brw_context *brw )
{
brw->base.set_framebuffer_state = brw_set_framebuffer_state;
- brw->base.set_framebuffer_state = brw_set_framebuffer_state;
+ brw->base.set_viewport_state = brw_set_viewport_state;
}
void brw_pipe_framebuffer_cleanup( struct brw_context *brw )
*/
static GLuint brw_flush_cmd( void )
{
- struct brw_mi_flush flush;
-
- return ;
-
- flush.opcode = CMD_MI_FLUSH;
- flush.pad = 0;
- flush.flags = BRW_FLUSH_STATE_CACHE;
- return *(GLuint *)&flush;
+ return ((CMD_MI_FLUSH << 16) | BRW_FLUSH_STATE_CACHE);
}
#include "brw_reg.h"
/** Waits on the query object's BO and totals the results for this query */
-static void
-brw_queryobj_get_results(struct brw_query_object *query)
+static boolean
+brw_query_get_result(struct pipe_context *pipe,
+ struct pipe_query *q,
+ boolean wait,
+ uint64_t *result)
{
- int i;
- uint64_t *results;
-
- if (query->bo == NULL)
- return;
+ struct brw_context *brw = brw_context(pipe);
+ struct brw_query_object *query = (struct brw_query_object *)q;
/* Map and count the pixels from the current query BO */
- dri_bo_map(query->bo, GL_FALSE);
- results = query->bo->virtual;
- for (i = query->first_index; i <= query->last_index; i++) {
- query->Base.Result += results[i * 2 + 1] - results[i * 2];
+ if (query->bo) {
+ int i;
+ uint64_t *map;
+
+ if (brw->sws->bo_is_busy(query->bo) && !wait)
+ return FALSE;
+
+ map = brw->sws->bo_map(query->bo, GL_FALSE);
+ if (map == NULL)
+ return FALSE;
+
+ for (i = query->first_index; i <= query->last_index; i++) {
+ query->result += map[i * 2 + 1] - map[i * 2];
+ }
+
+ brw->sws->bo_unmap(query->bo);
+ brw->sws->bo_unreference(query->bo);
+ query->bo = NULL;
}
- dri_bo_unmap(query->bo);
- brw->sws->bo_unreference(query->bo);
- query->bo = NULL;
+ *result = query->result;
+ return TRUE;
}
static struct pipe_query *
{
struct brw_query_object *query;
- switch (query->type) {
+ switch (type) {
case PIPE_QUERY_OCCLUSION_COUNTER:
query = CALLOC_STRUCT( brw_query_object );
if (query == NULL)
return NULL;
- return &query->Base;
+ return (struct pipe_query *)query;
default:
return NULL;
static void
brw_query_destroy(struct pipe_context *pipe, struct pipe_query *q)
{
+ struct brw_context *brw = brw_context(pipe);
struct brw_query_object *query = (struct brw_query_object *)q;
brw->sws->bo_unreference(query->bo);
}
static void
-brw_begin_query(struct pipe_context *pipe, struct pipe_query *q)
+brw_query_begin(struct pipe_context *pipe, struct pipe_query *q)
{
struct brw_context *brw = brw_context(pipe);
struct brw_query_object *query = (struct brw_query_object *)q;
/* Reset our driver's tracking of query state. */
brw->sws->bo_unreference(query->bo);
+ query->result = 0;
query->bo = NULL;
query->first_index = -1;
query->last_index = -1;
insert_at_head(&brw->query.active_head, query);
- brw->stats_wm++;
- brw->dirty.mesa |= PIPE_NEW_QUERY;
+ brw->query.stats_wm++;
+ brw->state.dirty.mesa |= PIPE_NEW_QUERY;
}
static void
-brw_end_query(struct pipe_context *pipe, struct pipe_query *q)
+brw_query_end(struct pipe_context *pipe, struct pipe_query *q)
{
struct brw_context *brw = brw_context(pipe);
struct brw_query_object *query = (struct brw_query_object *)q;
}
remove_from_list(query);
- brw->stats_wm--;
- brw->dirty.mesa |= PIPE_NEW_QUERY;
+ brw->query.stats_wm--;
+ brw->state.dirty.mesa |= PIPE_NEW_QUERY;
}
-static void brw_wait_query(struct pipe_context *pipe, struct pipe_query *q)
-{
- struct brw_query_object *query = (struct brw_query_object *)q;
-
- brw_queryobj_get_results(query);
- query->Base.Ready = GL_TRUE;
-}
-
-static void brw_check_query(struct pipe_context *pipe, struct pipe_query *q)
-{
- struct brw_query_object *query = (struct brw_query_object *)q;
-
- if (query->bo == NULL || !drm_intel_bo_busy(query->bo)) {
- brw_queryobj_get_results(query);
- query->Base.Ready = GL_TRUE;
- }
-}
+/***********************************************************************
+ * Internal functions and callbacks to implement queries
+ */
/** Called to set up the query BO and account for its aperture space */
void
foreach(query, &brw->query.active_head) {
if (query->bo != brw->query.bo) {
+ uint64_t tmp;
+
+ /* Propogate the results from this buffer to all of the
+ * active queries, as the bo is going away.
+ */
if (query->bo != NULL)
- brw_queryobj_get_results(query);
+ brw_query_get_result( &brw->base,
+ (struct pipe_query *)query,
+ FALSE,
+ &tmp );
+
brw->sws->bo_reference(brw->query.bo);
query->bo = brw->query.bo;
query->first_index = brw->query.index;
brw->query.index++;
}
-void brw_init_queryobj_functions(struct dd_function_table *functions)
+void brw_pipe_query_init( struct brw_context *brw )
{
- functions->NewQueryObject = brw_new_query_object;
- functions->DeleteQuery = brw_delete_query;
- functions->BeginQuery = brw_begin_query;
- functions->EndQuery = brw_end_query;
- functions->CheckQuery = brw_check_query;
- functions->WaitQuery = brw_wait_query;
+ brw->base.create_query = brw_query_create;
+ brw->base.destroy_query = brw_query_destroy;
+ brw->base.begin_query = brw_query_begin;
+ brw->base.end_query = brw_query_end;
+ brw->base.get_query_result = brw_query_get_result;
+}
+
+
+void brw_pipe_query_cleanup( struct brw_context *brw )
+{
+ /* Unreference brw->query.bo ??
+ */
}
{
struct brw_sampler_state *sampler = CALLOC_STRUCT(brw_sampler_state);
+ switch (key->minfilter) {
+ case GL_NEAREST:
+ sampler->ss0.min_filter = BRW_MAPFILTER_NEAREST;
+ sampler->ss0.mip_filter = BRW_MIPFILTER_NONE;
+ break;
+ case GL_LINEAR:
+ sampler->ss0.min_filter = BRW_MAPFILTER_LINEAR;
+ sampler->ss0.mip_filter = BRW_MIPFILTER_NONE;
+ break;
+ case GL_NEAREST_MIPMAP_NEAREST:
+ sampler->ss0.min_filter = BRW_MAPFILTER_NEAREST;
+ sampler->ss0.mip_filter = BRW_MIPFILTER_NEAREST;
+ break;
+ case GL_LINEAR_MIPMAP_NEAREST:
+ sampler->ss0.min_filter = BRW_MAPFILTER_LINEAR;
+ sampler->ss0.mip_filter = BRW_MIPFILTER_NEAREST;
+ break;
+ case GL_NEAREST_MIPMAP_LINEAR:
+ sampler->ss0.min_filter = BRW_MAPFILTER_NEAREST;
+ sampler->ss0.mip_filter = BRW_MIPFILTER_LINEAR;
+ break;
+ case GL_LINEAR_MIPMAP_LINEAR:
+ sampler->ss0.min_filter = BRW_MAPFILTER_LINEAR;
+ sampler->ss0.mip_filter = BRW_MIPFILTER_LINEAR;
+ break;
+ default:
+ break;
+ }
+
+ /* Set Anisotropy:
+ */
+ if (key->max_aniso > 1.0) {
+ sampler->ss0.min_filter = BRW_MAPFILTER_ANISOTROPIC;
+ sampler->ss0.mag_filter = BRW_MAPFILTER_ANISOTROPIC;
+
+ if (key->max_aniso > 2.0) {
+ sampler->ss3.max_aniso = MIN2((key->max_aniso - 2) / 2,
+ BRW_ANISORATIO_16);
+ }
+ }
+ else {
+ switch (key->magfilter) {
+ case GL_NEAREST:
+ sampler->ss0.mag_filter = BRW_MAPFILTER_NEAREST;
+ break;
+ case GL_LINEAR:
+ sampler->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
+ break;
+ default:
+ break;
+ }
+ }
+
+ sampler->ss1.r_wrap_mode = translate_wrap_mode(key->wrap_r);
+ sampler->ss1.s_wrap_mode = translate_wrap_mode(key->wrap_s);
+ sampler->ss1.t_wrap_mode = translate_wrap_mode(key->wrap_t);
+
+ /* Set LOD bias:
+ */
+ sampler->ss0.lod_bias = S_FIXED(CLAMP(key->lod_bias, -16, 15), 6);
+
+ sampler->ss0.lod_preclamp = 1; /* OpenGL mode */
+ sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */
+
+ /* Set shadow function:
+ */
+ if (key->comparemode == GL_COMPARE_R_TO_TEXTURE_ARB) {
+ /* Shadowing is "enabled" by emitting a particular sampler
+ * message (sample_c). So need to recompile WM program when
+ * shadow comparison is enabled on each/any texture unit.
+ */
+ sampler->ss0.shadow_function =
+ intel_translate_shadow_compare_func(key->comparefunc);
+ }
+
+ /* Set BaseMipLevel, MaxLOD, MinLOD:
+ */
+ sampler->ss0.base_level = U_FIXED(0, 1);
+
+ sampler->ss1.max_lod = U_FIXED(MIN2(MAX2(key->maxlod, 0), 13), 6);
+ sampler->ss1.min_lod = U_FIXED(MIN2(MAX2(key->minlod, 0), 13), 6);
return (void *)sampler;
}
- /* _NEW_BUFFERS */
- if (IS_965(brw->brw_screen->pci_id) &&
- !IS_G4X(brw->brw_screen->pci_id)) {
- for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
- struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
- struct intel_renderbuffer *irb = intel_renderbuffer(rb);
-
- /* The original gen4 hardware couldn't set up WM surfaces pointing
- * at an offset within a tile, which can happen when rendering to
- * anything but the base level of a texture or the +X face/0 depth.
- * This was fixed with the 4 Series hardware.
- *
- * For these original chips, you would have to make the depth and
- * color destination surfaces include information on the texture
- * type, LOD, face, and various limits to use them as a destination.
- * I would have done this, but there's also a nasty requirement that
- * the depth and the color surfaces all be of the same LOD, which
- * may be a worse requirement than this alignment. (Also, we may
- * want to just demote the texture to untiled, instead).
- */
- if (irb->region &&
- irb->region->tiling != I915_TILING_NONE &&
- (irb->region->draw_offset & 4095)) {
- DBG("FALLBACK: non-tile-aligned destination for tiled FBO\n");
- return GL_TRUE;
- }
+
+#include "pipe/p_screen.h"
+#include "brw_screen.h"
+
+struct brw_surface_id {
+ unsigned face:3;
+ unsigned zslice:13;
+ unsigned level:16;
+};
+
+static boolean need_linear_view( struct brw_screen *brw_screen,
+ struct brw_texture *brw_texture,
+ unsigned face,
+ unsigned level,
+ unsigned zslice )
+{
+#if 0
+ /* XXX: what about IDGNG?
+ */
+ if (!BRW_IS_G4X(brw->brw_screen->pci_id))
+ {
+ struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
+ struct intel_renderbuffer *irb = intel_renderbuffer(rb);
+
+ /* The original gen4 hardware couldn't set up WM surfaces pointing
+ * at an offset within a tile, which can happen when rendering to
+ * anything but the base level of a texture or the +X face/0 depth.
+ * This was fixed with the 4 Series hardware.
+ *
+ * For these original chips, you would have to make the depth and
+ * color destination surfaces include information on the texture
+ * type, LOD, face, and various limits to use them as a destination.
+ *
+ * This is easy in Gallium as surfaces are all backed by
+ * textures, but there's also a nasty requirement that the depth
+ * and the color surfaces all be of the same LOD, which is
+ * harder to get around as we can't look at a surface in
+ * isolation and decide if it's legal.
+ *
+ * Instead, end up being pessimistic and say that for i965,
+ * ... ??
+ */
+ if (brw_tex->tiling != I915_TILING_NONE &&
+ (brw_tex_image_offset(brw_tex, face, level, zslize) & 4095)) {
+ if (BRW_DEBUG & DEBUG_VIEW)
+ debug_printf("%s: need surface view for non-aligned tex image\n",
+ __FUNCTION__);
+ return GL_TRUE;
}
+ }
+#endif
+
+ /* Tiled 3d textures don't have subsets that look like 2d surfaces:
+ */
+
+ /* Everything else should be fine to render to in-place:
+ */
+ return GL_FALSE;
+}
+
+/* Look at all texture views and figure out if any of them need to be
+ * back-copied into the texture for sampling
+ */
+void brw_update_texture( struct pipe_screen *screen,
+ struct pipe_texture *texture )
+{
+ /* currently nothing to do */
+}
+
+
+static struct pipe_surface *create_linear_view( struct brw_screen *brw_screen,
+ struct brw_texture *brw_tex,
+ struct brw_surface_id id )
+{
+
+}
+
+static struct pipe_surface *create_in_place_view( struct brw_screen *brw_screen,
+ struct brw_texture *brw_tex,
+ struct brw_surface_id id )
+{
+ struct brw_surface *surface = CALLOC_STRUCT(brw_surface);
+ surface->id = id;
+
+}
+
+/* Get a surface which is view into a texture
+ */
+struct pipe_surface *brw_get_tex_surface(struct pipe_screen *screen,
+ struct pipe_texture *texture,
+ unsigned face, unsigned level,
+ unsigned zslice,
+ unsigned usage )
+{
+ struct brw_screen *bscreen = brw_screen(screen);
+ struct brw_surface_id id;
+
+ id.face = face;
+ id.level = level;
+ id.zslice = zslice;
+
+ if (need_linear_view(brw_screen, brw_tex, id))
+ type = BRW_VIEW_LINEAR;
+ else
+ type = BRW_VIEW_IN_PLACE;
+
+
+ foreach (surface, texture->views[type]) {
+ if (id.value == surface->id.value)
+ return surface;
+ }
+
+ switch (type) {
+ case BRW_VIEW_LINEAR:
+ surface = create_linear_view( texture, id, type );
+ break;
+ case BRW_VIEW_IN_PLACE:
+ surface = create_in_place_view( texture, id, type );
+ break;
+ default:
+ return NULL;
+ }
+
+ insert_at_head( texture->views[type], surface );
+ return surface;
+}
+
+
+void brw_tex_surface_destroy( struct pipe_surface *surface )
+{
+}
--- /dev/null
+/*
+ Copyright (C) Intel Corp. 2006. All Rights Reserved.
+ Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
+ develop this 3D driver.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice (including the
+ next paragraph) shall be included in all copies or substantial
+ portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+ **********************************************************************/
+ /*
+ * Authors:
+ * Keith Whitwell <keith@tungstengraphics.com>
+ */
+
+/* Code to layout images in a mipmap tree for i965.
+ */
+
+#include "brw_tex_layout.h"
+
+#define FILE_DEBUG_FLAG DEBUG_MIPTREE
+
+GLboolean brw_miptree_layout(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ uint32_t tiling)
+{
+ /* XXX: these vary depending on image format: */
+ /* GLint align_w = 4; */
+
+ switch (mt->target) {
+ case GL_TEXTURE_CUBE_MAP:
+ if (IS_IGDNG(brw->brw_screen->pci_id)) {
+ GLuint align_h = 2, align_w = 4;
+ GLuint level;
+ GLuint x = 0;
+ GLuint y = 0;
+ GLuint width = mt->width0;
+ GLuint height = mt->height0;
+ GLuint qpitch = 0;
+ GLuint y_pitch = 0;
+
+ mt->pitch = mt->width0;
+ intel_get_texture_alignment_unit(mt->internal_format, &align_w, &align_h);
+ y_pitch = ALIGN(height, align_h);
+
+ if (mt->compressed) {
+ mt->pitch = ALIGN(mt->width0, align_w);
+ }
+
+ if (mt->last_level != 0) {
+ GLuint mip1_width;
+
+ if (mt->compressed) {
+ mip1_width = ALIGN(minify(mt->width0), align_w)
+ + ALIGN(minify(minify(mt->width0)), align_w);
+ } else {
+ mip1_width = ALIGN(minify(mt->width0), align_w)
+ + minify(minify(mt->width0));
+ }
+
+ if (mip1_width > mt->pitch) {
+ mt->pitch = mip1_width;
+ }
+ }
+
+ mt->pitch = intel_miptree_pitch_align(intel, mt, tiling, mt->pitch);
+
+ if (mt->compressed) {
+ qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) / 4 * mt->pitch * mt->cpp;
+ mt->total_height = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) / 4 * 6;
+ } else {
+ qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) * mt->pitch * mt->cpp;
+ mt->total_height = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) * 6;
+ }
+
+ for (level = 0; level <= mt->last_level; level++) {
+ GLuint img_height;
+ GLuint nr_images = 6;
+ GLuint q = 0;
+
+ intel_miptree_set_level_info(mt, level, nr_images, x, y, width,
+ height, 1);
+
+ for (q = 0; q < nr_images; q++)
+ intel_miptree_set_image_offset_ex(mt, level, q, x, y, q * qpitch);
+
+ if (mt->compressed)
+ img_height = MAX2(1, height/4);
+ else
+ img_height = ALIGN(height, align_h);
+
+ if (level == 1) {
+ x += ALIGN(width, align_w);
+ }
+ else {
+ y += img_height;
+ }
+
+ width = minify(width);
+ height = minify(height);
+ }
+
+ break;
+ }
+
+ case GL_TEXTURE_3D: {
+ GLuint width = mt->width0;
+ GLuint height = mt->height0;
+ GLuint depth = mt->depth0;
+ GLuint pack_x_pitch, pack_x_nr;
+ GLuint pack_y_pitch;
+ GLuint level;
+ GLuint align_h = 2;
+ GLuint align_w = 4;
+
+ mt->total_height = 0;
+ intel_get_texture_alignment_unit(mt->internal_format, &align_w, &align_h);
+
+ if (mt->compressed) {
+ mt->pitch = ALIGN(width, align_w);
+ pack_y_pitch = (height + 3) / 4;
+ } else {
+ mt->pitch = intel_miptree_pitch_align (intel, mt, tiling, mt->width0);
+ pack_y_pitch = ALIGN(mt->height0, align_h);
+ }
+
+ pack_x_pitch = width;
+ pack_x_nr = 1;
+
+ for (level = 0 ; level <= mt->last_level ; level++) {
+ GLuint nr_images = mt->target == GL_TEXTURE_3D ? depth : 6;
+ GLint x = 0;
+ GLint y = 0;
+ GLint q, j;
+
+ intel_miptree_set_level_info(mt, level, nr_images,
+ 0, mt->total_height,
+ width, height, depth);
+
+ for (q = 0; q < nr_images;) {
+ for (j = 0; j < pack_x_nr && q < nr_images; j++, q++) {
+ intel_miptree_set_image_offset(mt, level, q, x, y);
+ x += pack_x_pitch;
+ }
+
+ x = 0;
+ y += pack_y_pitch;
+ }
+
+
+ mt->total_height += y;
+ width = minify(width);
+ height = minify(height);
+ depth = minify(depth);
+
+ if (mt->compressed) {
+ pack_y_pitch = (height + 3) / 4;
+
+ if (pack_x_pitch > ALIGN(width, align_w)) {
+ pack_x_pitch = ALIGN(width, align_w);
+ pack_x_nr <<= 1;
+ }
+ } else {
+ if (pack_x_pitch > 4) {
+ pack_x_pitch >>= 1;
+ pack_x_nr <<= 1;
+ assert(pack_x_pitch * pack_x_nr <= mt->pitch);
+ }
+
+ if (pack_y_pitch > 2) {
+ pack_y_pitch >>= 1;
+ pack_y_pitch = ALIGN(pack_y_pitch, align_h);
+ }
+ }
+
+ }
+ /* The 965's sampler lays cachelines out according to how accesses
+ * in the texture surfaces run, so they may be "vertical" through
+ * memory. As a result, the docs say in Surface Padding Requirements:
+ * Sampling Engine Surfaces that two extra rows of padding are required.
+ * We don't know of similar requirements for pre-965, but given that
+ * those docs are silent on padding requirements in general, let's play
+ * it safe.
+ */
+ if (mt->target == GL_TEXTURE_CUBE_MAP)
+ mt->total_height += 2;
+ break;
+ }
+
+ default:
+ i945_miptree_layout_2d(intel, mt, tiling);
+ break;
+ }
+ DBG("%s: %dx%dx%d - sz 0x%x\n", __FUNCTION__,
+ mt->pitch,
+ mt->total_height,
+ mt->cpp,
+ mt->pitch * mt->total_height * mt->cpp );
+
+ return GL_TRUE;
+}
+
* Keith Whitwell <keith@tungstengraphics.com>
*/
+#include "pipe/p_state.h"
#include "brw_batchbuffer.h"
-
#include "brw_defines.h"
#include "brw_context.h"
+#include "brw_pipe_rast.h"
#include "brw_eu.h"
#include "brw_util.h"
#include "brw_sf.h"
struct brw_sf_compile c;
const GLuint *program;
GLuint program_size;
- GLuint i, idx;
memset(&c, 0, sizeof(c));
brw_init_compile(brw, &c.func);
c.key = *key;
- c.nr_attrs = util_count_bits(c.key.attrs);
+ c.nr_attrs = c.key.nr_attrs;
c.nr_attr_regs = (c.nr_attrs+1)/2;
c.nr_setup_attrs = c.key.nr_attrs;
c.nr_setup_regs = (c.nr_setup_attrs+1)/2;
c.prog_data.urb_read_length = c.nr_attr_regs;
c.prog_data.urb_entry_size = c.nr_setup_regs * 2;
- /* Construct map from attribute number to position in the vertex.
- */
- for (i = idx = 0; i < VERT_RESULT_MAX; i++)
- if (c.key.attrs & (1<<i)) {
- c.attr_to_idx[i] = idx;
- c.idx_to_attr[idx] = i;
- if (i >= VERT_RESULT_TEX0 && i <= VERT_RESULT_TEX7) {
- c.point_attrs[i].CoordReplace =
- ctx->Point.CoordReplace[i - VERT_RESULT_TEX0];
- }
- else {
- c.point_attrs[i].CoordReplace = GL_FALSE;
- }
- idx++;
- }
/* Which primitive? Or all three?
*/
/* Calculate interpolants for triangle and line rasterization.
*/
-static void upload_sf_prog(struct brw_context *brw)
+static int upload_sf_prog(struct brw_context *brw)
{
struct brw_sf_prog_key key;
/* Populate the key, noting state dependencies:
*/
/* CACHE_NEW_VS_PROG */
- key.attrs = brw->vs.prog_data->nr_outputs_written;
+ key.nr_attrs = brw->curr.vertex_shader->info.file_max[TGSI_FILE_OUTPUT] + 1;
+
+
+ /* XXX: this is probably where the mapping between vertex shader
+ * outputs and fragment shader inputs should be handled. Assume
+ * for now 1:1 correspondance.
+ *
+ * XXX: scan frag shader inputs to work out linear vs. perspective
+ * interpolation below.
+ *
+ * XXX: as long as we're hard-wiring, is eg. position required to
+ * be linear?
+ */
+ key.linear_attrs = 0;
+ key.persp_attrs = (1 << key.nr_attrs) - 1;
/* BRW_NEW_REDUCED_PRIMITIVE */
switch (brw->reduced_primitive) {
- case GL_TRIANGLES:
- /* NOTE: We just use the edgeflag attribute as an indicator that
- * unfilled triangles are active. We don't actually do the
- * edgeflag testing here, it is already done in the clip
- * program.
+ case PIPE_PRIM_TRIANGLES:
+ /* PIPE_NEW_RAST
*/
- if (key.attrs & (1<<VERT_RESULT_EDGE))
+ if (brw->curr.rast->templ.fill_cw != PIPE_POLYGON_MODE_FILL ||
+ brw->curr.rast->templ.fill_ccw != PIPE_POLYGON_MODE_FILL)
key.primitive = SF_UNFILLED_TRIS;
else
key.primitive = SF_TRIANGLES;
break;
- case GL_LINES:
+ case PIPE_PRIM_LINES:
key.primitive = SF_LINES;
break;
- case GL_POINTS:
+ case PIPE_PRIM_POINTS:
key.primitive = SF_POINTS;
break;
}
- key.do_point_sprite = ctx->Point.PointSprite;
- key.SpriteOrigin = ctx->Point.SpriteOrigin;
- /* _NEW_LIGHT */
- key.do_flat_shading = (ctx->Light.ShadeModel == GL_FLAT);
- key.do_twoside_color = (ctx->Light.Enabled && ctx->Light.Model.TwoSide);
+ key.do_point_sprite = brw->curr.rast->templ.point_sprite;
+ key.sprite_origin_lower_left = 0; /* XXX: ctx->Point.SpriteOrigin - fix rast state */
+ key.do_flat_shading = brw->curr.rast->templ.flatshade;
+ key.do_twoside_color = brw->curr.rast->templ.light_twoside;
- /* _NEW_HINT */
- key.linear_color = 0;
-
- /* _NEW_POLYGON */
if (key.do_twoside_color) {
- /* If we're rendering to a FBO, we have to invert the polygon
- * face orientation, just as we invert the viewport in
- * sf_unit_create_from_key(). ctx->DrawBuffer->Name will be
- * nonzero if we're rendering to such an FBO.
- */
- key.frontface_ccw = (ctx->Polygon.FrontFace == GL_CCW) ^ (ctx->DrawBuffer->Name != 0);
+ key.frontface_ccw = (brw->curr.rast->templ.front_winding ==
+ PIPE_WINDING_CCW);
}
brw->sws->bo_unreference(brw->sf.prog_bo);
&brw->sf.prog_data);
if (brw->sf.prog_bo == NULL)
compile_sf_prog( brw, &key );
+
+ return 0;
}
const struct brw_tracked_state brw_sf_prog = {
.dirty = {
- .mesa = (_NEW_HINT | _NEW_LIGHT | _NEW_POLYGON | _NEW_POINT),
+ .mesa = (PIPE_NEW_RAST | PIPE_NEW_VERTEX_SHADER),
.brw = (BRW_NEW_REDUCED_PRIMITIVE),
- .cache = CACHE_NEW_VS_PROG
+ .cache = 0
},
.prepare = upload_sf_prog
};
*/
GLuint persp_attrs:32;
GLuint linear_attrs:32;
+ GLuint point_coord_replace_attrs:32;
+ GLuint nr_attrs:8;
GLuint primitive:2;
GLuint do_twoside_color:1;
GLuint do_flat_shading:1;
GLuint frontface_ccw:1;
GLuint do_point_sprite:1;
GLuint sprite_origin_lower_left:1;
- GLuint pad:25;
+ GLuint pad:17;
+
+ GLuint attr_col0:8;
+ GLuint attr_col1:8;
+ GLuint attr_bfc0:8;
+ GLuint attr_bfc1:8;
};
struct brw_sf_point_tex {
GLuint nr_setup_attrs;
GLuint nr_setup_regs;
- GLubyte attr_to_idx[VERT_RESULT_MAX];
- GLubyte idx_to_attr[VERT_RESULT_MAX];
- struct brw_sf_point_tex point_attrs[VERT_RESULT_MAX];
+ GLuint point_coord_replace_mask;
};
struct brw_reg vert,
GLuint attr)
{
- GLuint off = c->attr_to_idx[attr] / 2;
- GLuint sub = c->attr_to_idx[attr] % 2;
+ GLuint off = attr / 2;
+ GLuint sub = attr % 2;
return brw_vec4_grf(vert.nr + off, sub * 4);
}
-static GLboolean have_attr(struct brw_sf_compile *c,
- GLuint attr)
-{
- return (c->key.attrs & (1<<attr)) ? 1 : 0;
-}
/***********************************************************************
* Twoside lighting
struct brw_reg vert )
{
struct brw_compile *p = &c->func;
- GLuint i;
- for (i = 0; i < 2; i++) {
- if (have_attr(c, VERT_RESULT_COL0+i) &&
- have_attr(c, VERT_RESULT_BFC0+i))
- brw_MOV(p,
- get_vert_attr(c, vert, VERT_RESULT_COL0+i),
- get_vert_attr(c, vert, VERT_RESULT_BFC0+i));
- }
+ if (c->key.attr_col0 && c->key.attr_bfc0)
+ brw_MOV(p,
+ get_vert_attr(c, vert, c->key.attr_col0),
+ get_vert_attr(c, vert, c->key.attr_bfc0));
+
+ if (c->key.attr_col1 && c->key.attr_bfc1)
+ brw_MOV(p,
+ get_vert_attr(c, vert, c->key.attr_col1),
+ get_vert_attr(c, vert, c->key.attr_bfc1));
}
* for user-supplied vertex programs, as t_vp_build.c always does
* the right thing.
*/
- if (!(have_attr(c, VERT_RESULT_COL0) && have_attr(c, VERT_RESULT_BFC0)) &&
- !(have_attr(c, VERT_RESULT_COL1) && have_attr(c, VERT_RESULT_BFC1)))
+ if (!(c->key.attr_col0 && c->key.attr_bfc0) &&
+ !(c->key.attr_col1 && c->key.attr_bfc1))
return;
/* Need to use BRW_EXECUTE_4 and also do an 4-wide compare in order
struct brw_reg src)
{
struct brw_compile *p = &c->func;
- GLuint i;
- for (i = VERT_RESULT_COL0; i <= VERT_RESULT_COL1; i++) {
- if (have_attr(c,i))
- brw_MOV(p,
- get_vert_attr(c, dst, i),
- get_vert_attr(c, src, i));
- }
+ if (c->key.attr_col0)
+ brw_MOV(p,
+ get_vert_attr(c, dst, c->key.attr_col0),
+ get_vert_attr(c, src, c->key.attr_col0));
+
+ if (c->key.attr_col1)
+ brw_MOV(p,
+ get_vert_attr(c, dst, c->key.attr_col1),
+ get_vert_attr(c, src, c->key.attr_col1));
+
}
{
struct brw_compile *p = &c->func;
struct brw_reg ip = brw_ip_reg();
- GLuint nr = util_count_bits(c->key.attrs & VERT_RESULT_COLOR_BITS);
GLuint jmpi = 1;
+ GLuint nr = 0;
- if (!nr)
+ if (c->key.attr_col0)
+ nr++;
+
+ if (c->key.attr_col1)
+ nr++;
+
+ if (nr == 0)
return;
/* Already done in clip program:
{
struct brw_compile *p = &c->func;
struct brw_reg ip = brw_ip_reg();
- GLuint nr = util_count_bits(c->key.attrs & VERT_RESULT_COLOR_BITS);
GLuint jmpi = 1;
+ GLuint nr = 0;
+
+ if (c->key.attr_col0)
+ nr++;
+
+ if (c->key.attr_col1)
+ nr++;
- if (!nr)
+ if (nr == 0)
return;
/* Already done in clip program:
*pc_linear = 0;
*pc = 0xf;
- if (persp_mask & (1 << c->idx_to_attr[reg*2]))
+ if (persp_mask & (1 << (reg*2)))
*pc_persp = 0xf;
- if (linear_mask & (1 << c->idx_to_attr[reg*2]))
+ if (linear_mask & (1 << (reg*2)))
*pc_linear = 0xf;
/* Maybe only processs one attribute on the final round:
if (reg*2+1 < c->nr_setup_attrs) {
*pc |= 0xf0;
- if (persp_mask & (1 << c->idx_to_attr[reg*2+1]))
+ if (persp_mask & (1 << (reg*2+1)))
*pc_persp |= 0xf0;
- if (linear_mask & (1 << c->idx_to_attr[reg*2+1]))
+ if (linear_mask & (1 << (reg*2+1)))
*pc_linear |= 0xf0;
}
alloc_regs(c);
copy_z_inv_w(c);
+
for (i = 0; i < c->nr_setup_regs; i++)
{
- struct brw_sf_point_tex *tex = &c->point_attrs[c->idx_to_attr[2*i]];
+ /* XXX: only seems to check point_coord_replace_attrs for every
+ * second attribute?!?
+ */
+ boolean coord_replace = !!(c->key.point_coord_replace_attrs & (1<<(2*i)));
struct brw_reg a0 = offset(c->vert[0], i);
GLushort pc, pc_persp, pc_linear;
GLboolean last = calculate_masks(c, i, &pc, &pc_persp, &pc_linear);
if (pc_persp)
{
- if (!tex->CoordReplace) {
- brw_set_predicate_control_flag_value(p, pc_persp);
- brw_MUL(p, a0, a0, c->inv_w[0]);
- }
+ if (coord_replace) {
+ brw_set_predicate_control_flag_value(p, pc_persp);
+ brw_MUL(p, a0, a0, c->inv_w[0]);
+ }
}
- if (tex->CoordReplace) {
- /* Caculate 1.0/PointWidth */
- brw_math(&c->func,
+ if (coord_replace) {
+ /* Caculate 1.0/PointWidth */
+ brw_math(&c->func,
c->tmp,
BRW_MATH_FUNCTION_INV,
BRW_MATH_SATURATE_NONE,
BRW_MATH_DATA_SCALAR,
BRW_MATH_PRECISION_FULL);
- if (c->key.SpriteOrigin == GL_LOWER_LEFT) {
- brw_MUL(p, c->m1Cx, c->tmp, c->inv_w[0]);
- brw_MOV(p, vec1(suboffset(c->m1Cx, 1)), brw_imm_f(0.0));
- brw_MUL(p, c->m2Cy, c->tmp, negate(c->inv_w[0]));
- brw_MOV(p, vec1(suboffset(c->m2Cy, 0)), brw_imm_f(0.0));
- } else {
- brw_MUL(p, c->m1Cx, c->tmp, c->inv_w[0]);
- brw_MOV(p, vec1(suboffset(c->m1Cx, 1)), brw_imm_f(0.0));
- brw_MUL(p, c->m2Cy, c->tmp, c->inv_w[0]);
- brw_MOV(p, vec1(suboffset(c->m2Cy, 0)), brw_imm_f(0.0));
- }
- } else {
- brw_MOV(p, c->m1Cx, brw_imm_ud(0));
- brw_MOV(p, c->m2Cy, brw_imm_ud(0));
+ if (c->key.sprite_origin_lower_left) {
+ brw_MUL(p, c->m1Cx, c->tmp, c->inv_w[0]);
+ brw_MOV(p, vec1(suboffset(c->m1Cx, 1)), brw_imm_f(0.0));
+ brw_MUL(p, c->m2Cy, c->tmp, negate(c->inv_w[0]));
+ brw_MOV(p, vec1(suboffset(c->m2Cy, 0)), brw_imm_f(0.0));
+ }
+ else {
+ brw_MUL(p, c->m1Cx, c->tmp, c->inv_w[0]);
+ brw_MOV(p, vec1(suboffset(c->m1Cx, 1)), brw_imm_f(0.0));
+ brw_MUL(p, c->m2Cy, c->tmp, c->inv_w[0]);
+ brw_MOV(p, vec1(suboffset(c->m2Cy, 0)), brw_imm_f(0.0));
+ }
+ }
+ else {
+ brw_MOV(p, c->m1Cx, brw_imm_ud(0));
+ brw_MOV(p, c->m2Cy, brw_imm_ud(0));
}
{
brw_set_predicate_control_flag_value(p, pc);
- if (tex->CoordReplace) {
- if (c->key.sprite_origin_lower_left) {
- brw_MUL(p, c->m3C0, c->inv_w[0], brw_imm_f(1.0));
- brw_MOV(p, vec1(suboffset(c->m3C0, 0)), brw_imm_f(0.0));
- }
- else
- brw_MOV(p, c->m3C0, brw_imm_f(0.0));
- } else {
- brw_MOV(p, c->m3C0, a0); /* constant value */
+ if (coord_replace) {
+ if (c->key.sprite_origin_lower_left) {
+ brw_MUL(p, c->m3C0, c->inv_w[0], brw_imm_f(1.0));
+ brw_MOV(p, vec1(suboffset(c->m3C0, 0)), brw_imm_f(0.0));
+ }
+ else {
+ brw_MOV(p, c->m3C0, brw_imm_f(0.0));
+ }
+ }
+ else {
+ brw_MOV(p, c->m3C0, a0); /* constant value */
}
/* Copy m0..m3 to URB.
* Keith Whitwell <keith@tungstengraphics.com>
*/
+#include "util/u_math.h"
+#include "pipe/p_state.h"
#include "brw_context.h"
#include "brw_state.h"
#include "brw_defines.h"
+#include "brw_debug.h"
+#include "brw_pipe_rast.h"
-static void upload_sf_vp(struct brw_context *brw)
+static int upload_sf_vp(struct brw_context *brw)
{
- const GLfloat depth_scale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
+ const struct pipe_viewport_state *vp = &brw->curr.vp;
+ const struct pipe_scissor_state *scissor = &brw->curr.scissor;
struct brw_sf_viewport sfv;
- GLfloat y_scale, y_bias;
- const GLfloat *v = ctx->Viewport._WindowMap.m;
memset(&sfv, 0, sizeof(sfv));
- y_scale = 1.0;
- y_bias = 0;
+ /* PIPE_NEW_VIEWPORT, PIPE_NEW_SCISSOR */
- /* _NEW_VIEWPORT */
+ sfv.viewport.m00 = vp->scale[0];
+ sfv.viewport.m11 = vp->scale[1];
+ sfv.viewport.m22 = vp->scale[2];
+ sfv.viewport.m30 = vp->translate[0];
+ sfv.viewport.m31 = vp->translate[1];
+ sfv.viewport.m32 = vp->translate[2];
- sfv.viewport.m00 = v[MAT_SX];
- sfv.viewport.m11 = v[MAT_SY] * y_scale;
- sfv.viewport.m22 = v[MAT_SZ] * depth_scale;
- sfv.viewport.m30 = v[MAT_TX];
- sfv.viewport.m31 = v[MAT_TY] * y_scale + y_bias;
- sfv.viewport.m32 = v[MAT_TZ] * depth_scale;
-
- /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT
- * for DrawBuffer->_[XY]{min,max}
- */
-
- /* The scissor only needs to handle the intersection of drawable and
- * scissor rect.
- *
- * Note that the hardware's coordinates are inclusive, while Mesa's min is
- * inclusive but max is exclusive.
- */
- /* Y=0=bottom */
- sfv.scissor.xmin = ctx->DrawBuffer->_Xmin;
- sfv.scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
- sfv.scissor.ymin = ctx->DrawBuffer->_Ymin;
- sfv.scissor.ymax = ctx->DrawBuffer->_Ymax - 1;
+ sfv.scissor.xmin = scissor->minx;
+ sfv.scissor.xmax = scissor->maxx; /* -1 ?? */
+ sfv.scissor.ymin = scissor->miny;
+ sfv.scissor.ymax = scissor->maxy; /* -1 ?? */
brw->sws->bo_unreference(brw->sf.vp_bo);
brw->sf.vp_bo = brw_cache_data( &brw->cache, BRW_SF_VP, &sfv, NULL, 0 );
+
+ return 0;
}
const struct brw_tracked_state brw_sf_vp = {
.dirty = {
- .mesa = (_NEW_VIEWPORT |
- _NEW_SCISSOR |
- _NEW_BUFFERS),
+ .mesa = (PIPE_NEW_VIEWPORT |
+ PIPE_NEW_SCISSOR),
.brw = 0,
.cache = 0
},
struct brw_sf_unit_key {
unsigned int total_grf;
unsigned int urb_entry_read_length;
-
unsigned int nr_urb_entries, urb_size, sfsize;
-
- GLenum front_face, cull_face, provoking_vertex;
+
unsigned scissor:1;
unsigned line_smooth:1;
unsigned point_sprite:1;
unsigned point_attenuated:1;
- unsigned render_to_fbo:1;
+ unsigned front_face:2;
+ unsigned cull_mode:2;
+ unsigned flatshade_first:1;
+ unsigned gl_rasterization_rules:1;
+ unsigned line_last_pixel_enable:1;
float line_width;
float point_size;
};
static void
sf_unit_populate_key(struct brw_context *brw, struct brw_sf_unit_key *key)
{
+ const struct pipe_rasterizer_state *rast = &brw->curr.rast->templ;
memset(key, 0, sizeof(*key));
/* CACHE_NEW_SF_PROG */
key->urb_size = brw->urb.vsize;
key->sfsize = brw->urb.sfsize;
- key->scissor = ctx->Scissor.Enabled;
- key->front_face = ctx->Polygon.FrontFace;
-
- if (ctx->Polygon.CullFlag)
- key->cull_face = ctx->Polygon.CullFaceMode;
- else
- key->cull_face = GL_NONE;
-
- key->line_width = ctx->Line.Width;
- key->line_smooth = ctx->Line.SmoothFlag;
-
- key->point_sprite = ctx->Point.PointSprite;
- key->point_size = CLAMP(ctx->Point.Size, ctx->Point.MinSize, ctx->Point.MaxSize);
- key->point_attenuated = ctx->Point._Attenuated;
-
- /* _NEW_LIGHT */
- key->provoking_vertex = ctx->Light.ProvokingVertex;
-
- key->render_to_fbo = 1;
+ /* PIPE_NEW_RAST */
+ key->scissor = rast->scissor;
+ key->front_face = rast->front_winding;
+ key->cull_mode = rast->cull_mode;
+ key->line_smooth = rast->line_smooth;
+ key->line_width = rast->line_width;
+ key->flatshade_first = rast->flatshade_first;
+ key->line_last_pixel_enable = rast->line_last_pixel;
+ key->gl_rasterization_rules = rast->gl_rasterization_rules;
+
+ key->point_sprite = rast->point_sprite;
+ key->point_attenuated = rast->point_size_per_vertex;
+
+ key->point_size = CLAMP(rast->point_size,
+ rast->point_size_min,
+ rast->point_size_max);
}
static struct brw_winsys_buffer *
int chipset_max_threads;
memset(&sf, 0, sizeof(sf));
- sf.thread0.grf_reg_count = ALIGN(key->total_grf, 16) / 16 - 1;
+ sf.thread0.grf_reg_count = align(key->total_grf, 16) / 16 - 1;
sf.thread0.kernel_start_pointer = brw->sf.prog_bo->offset >> 6; /* reloc */
sf.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
sf.thread4.max_threads = MIN2(chipset_max_threads, key->nr_urb_entries) - 1;
- if (INTEL_DEBUG & DEBUG_SINGLE_THREAD)
+ if (BRW_DEBUG & DEBUG_SINGLE_THREAD)
sf.thread4.max_threads = 0;
- if (INTEL_DEBUG & DEBUG_STATS)
+ if (BRW_DEBUG & DEBUG_STATS)
sf.thread4.stats_enable = 1;
/* CACHE_NEW_SF_VP */
sf.sf5.viewport_transform = 1;
- /* _NEW_SCISSOR */
if (key->scissor)
sf.sf6.scissor = 1;
- /* _NEW_POLYGON */
- if (key->front_face == GL_CCW)
+ if (key->front_face == PIPE_WINDING_CCW)
sf.sf5.front_winding = BRW_FRONTWINDING_CCW;
else
sf.sf5.front_winding = BRW_FRONTWINDING_CW;
- switch (key->cull_face) {
- case GL_FRONT:
- sf.sf6.cull_mode = BRW_CULLMODE_FRONT;
+ switch (key->cull_mode) {
+ case PIPE_WINDING_CCW:
+ case PIPE_WINDING_CW:
+ sf.sf6.cull_mode = (key->front_face == key->cull_mode ?
+ BRW_CULLMODE_FRONT :
+ BRW_CULLMODE_BACK);
break;
- case GL_BACK:
- sf.sf6.cull_mode = BRW_CULLMODE_BACK;
- break;
- case GL_FRONT_AND_BACK:
+ case PIPE_WINDING_BOTH:
sf.sf6.cull_mode = BRW_CULLMODE_BOTH;
break;
- case GL_NONE:
+ case PIPE_WINDING_NONE:
sf.sf6.cull_mode = BRW_CULLMODE_NONE;
break;
default:
assert(0);
+ sf.sf6.cull_mode = BRW_CULLMODE_NONE;
break;
}
else if (sf.sf6.line_width <= 0x2)
sf.sf6.line_width = 0;
- /* _NEW_BUFFERS */
- key->render_to_fbo = 1;
- if (!key->render_to_fbo) {
+ /* XXX: gl_rasterization_rules? something else?
+ */
+ if (0) {
/* Rendering to an OpenGL window */
sf.sf6.point_rast_rule = BRW_RASTRULE_UPPER_RIGHT;
}
/* might be BRW_NEW_PRIMITIVE if we have to adjust pv for polygons:
*/
- if (key->provoking_vertex == GL_LAST_VERTEX_CONVENTION) {
+ if (!key->flatshade_first) {
sf.sf7.trifan_pv = 2;
sf.sf7.linestrip_pv = 1;
sf.sf7.tristrip_pv = 2;
sf.sf7.linestrip_pv = 0;
sf.sf7.tristrip_pv = 0;
}
- sf.sf7.line_last_pixel_enable = 0;
+
+ sf.sf7.line_last_pixel_enable = key->line_last_pixel_enable;
/* Set bias for OpenGL rasterization rules:
*/
- sf.sf6.dest_org_vbias = 0x8;
- sf.sf6.dest_org_hbias = 0x8;
+ if (key->gl_rasterization_rules) {
+ sf.sf6.dest_org_vbias = 0x8;
+ sf.sf6.dest_org_hbias = 0x8;
+ }
+ else {
+ sf.sf6.dest_org_vbias = 0x0;
+ sf.sf6.dest_org_hbias = 0x0;
+ }
bo = brw_upload_cache(&brw->cache, BRW_SF_UNIT,
key, sizeof(*key),
* something loaded through the GPE (L2 ISC), so it's INSTRUCTION domain.
*/
/* Emit SF program relocation */
- dri_bo_emit_reloc(bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- sf.thread0.grf_reg_count << 1,
- offsetof(struct brw_sf_unit_state, thread0),
- brw->sf.prog_bo);
+ brw->sws->bo_emit_reloc(bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ sf.thread0.grf_reg_count << 1,
+ offsetof(struct brw_sf_unit_state, thread0),
+ brw->sf.prog_bo);
/* Emit SF viewport relocation */
- dri_bo_emit_reloc(bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- sf.sf5.front_winding | (sf.sf5.viewport_transform << 1),
- offsetof(struct brw_sf_unit_state, sf5),
- brw->sf.vp_bo);
+ brw->sws->bo_emit_reloc(bo,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ sf.sf5.front_winding | (sf.sf5.viewport_transform << 1),
+ offsetof(struct brw_sf_unit_state, sf5),
+ brw->sf.vp_bo);
return bo;
}
-static void upload_sf_unit( struct brw_context *brw )
+static int upload_sf_unit( struct brw_context *brw )
{
struct brw_sf_unit_key key;
struct brw_winsys_buffer *reloc_bufs[2];
if (brw->sf.state_bo == NULL) {
brw->sf.state_bo = sf_unit_create_from_key(brw, &key, reloc_bufs);
}
+ return 0;
}
const struct brw_tracked_state brw_sf_unit = {
.dirty = {
- .mesa = (_NEW_POLYGON |
- _NEW_LIGHT |
- _NEW_LINE |
- _NEW_POINT |
- _NEW_SCISSOR |
- _NEW_BUFFERS),
+ .mesa = (PIPE_NEW_RAST),
.brw = BRW_NEW_URB_FENCE,
.cache = (CACHE_NEW_SF_VP |
CACHE_NEW_SF_PROG)
void brw_destroy_batch_cache( struct brw_context *brw );
void brw_clear_batch_cache( struct brw_context *brw );
-/* brw_wm_surface_state.c */
+/***********************************************************************
+ * brw_wm_surface_state.c
+ */
struct brw_winsys_buffer *
brw_create_constant_surface( struct brw_context *brw,
struct brw_surface_key *key );
+/***********************************************************************
+ * brw_state_debug.c
+ */
+void brw_update_dirty_counts( unsigned mesa,
+ unsigned brw,
+ unsigned cache );
+
+
+
#endif
struct brw_cached_batch_item *item = brw->cached_batch_items;
struct header *newheader = (struct header *)data;
- if (brw->emit_state_always) {
+ if (brw->flags.always_emit_state) {
brw_batchbuffer_data(brw->batch, data, sz, IGNORE_CLIPRECTS);
return GL_TRUE;
}
if (item->sz == sz && memcmp(item->header, newheader, sz) == 0)
return GL_FALSE;
if (item->sz != sz) {
- _mesa_free(item->header);
- item->header = _mesa_malloc(sz);
+ FREE(item->header);
+ item->header = MALLOC(sz);
item->sz = sz;
}
goto emit;
assert(!item);
item = CALLOC_STRUCT(brw_cached_batch_item);
- item->header = _mesa_malloc(sz);
+ item->header = MALLOC(sz);
item->sz = sz;
item->next = brw->cached_batch_items;
brw->cached_batch_items = item;
* only one of the two buffers referenced gets put into the offset, and the
* incorrect program is run for the other instance.
*/
+#include "util/u_memory.h"
+#include "brw_debug.h"
#include "brw_state.h"
#include "brw_batchbuffer.h"
if (bo == cache->last_bo[cache_id])
return; /* no change */
- brw->sws->bo_unreference(cache->last_bo[cache_id]);
+ cache->sws->bo_unreference(cache->last_bo[cache_id]);
cache->last_bo[cache_id] = bo;
- brw->sws->bo_reference(cache->last_bo[cache_id]);
+ cache->sws->bo_reference(cache->last_bo[cache_id]);
cache->brw->state.dirty.cache |= 1 << cache_id;
}
for (c = cache->items[hash % cache->size]; c; c = c->next)
bucketcount++;
- fprintf(stderr, "bucket %d/%d = %d/%d items\n", hash % cache->size,
+ debug_printf("bucket %d/%d = %d/%d items\n", hash % cache->size,
cache->size, bucketcount, cache->n_items);
#endif
GLuint size, i;
size = cache->size * 3;
- items = (struct brw_cache_item**) _mesa_calloc(size * sizeof(*items));
+ items = (struct brw_cache_item**) CALLOC(size, sizeof(*items));
for (i = 0; i < cache->size; i++)
for (c = cache->items[i]; c; c = next) {
update_cache_last(cache, cache_id, item->bo);
- brw->sws->bo_reference(item->bo);
+ cache->sws->bo_reference(item->bo);
return item->bo;
}
struct brw_winsys_buffer *bo;
int i;
- /* Create the buffer object to contain the data */
- bo = brw->sws->bo_alloc(cache->sws,
- cache->buffer_type[cache_id], data_size, 1 << 6);
+ /* Create the buffer object to contain the data. For now, use a
+ * single buffer type to describe all cached state atoms. Later,
+ * may want to take advantage of hardware distinctions between
+ * these various entities.
+ */
+ bo = cache->sws->bo_alloc(cache->sws,
+ BRW_BUFFER_TYPE_STATE_CACHE,
+ data_size, 1 << 6);
/* Set up the memory containing the key, aux_data, and reloc_bufs */
- tmp = _mesa_malloc(key_size + aux_size + relocs_size);
+ tmp = MALLOC(key_size + aux_size + relocs_size);
memcpy(tmp, key, key_size);
memcpy(tmp + key_size, aux, cache->aux_size[cache_id]);
memcpy(tmp + key_size + aux_size, reloc_bufs, relocs_size);
for (i = 0; i < nr_reloc_bufs; i++) {
if (reloc_bufs[i] != NULL)
- brw->sws->bo_reference(reloc_bufs[i]);
+ cache->sws->bo_reference(reloc_bufs[i]);
}
item->cache_id = cache_id;
item->nr_reloc_bufs = nr_reloc_bufs;
item->bo = bo;
- brw->sws->bo_reference(bo);
+ cache->sws->bo_reference(bo);
item->data_size = data_size;
if (cache->n_items > cache->size * 1.5)
*(void **)aux_return = (void *)((char *)item->key + item->key_size);
}
- if (INTEL_DEBUG & DEBUG_STATE)
- _mesa_printf("upload %s: %d bytes to cache id %d\n",
+ if (BRW_DEBUG & DEBUG_STATE)
+ debug_printf("upload %s: %d bytes to cache id %d\n",
cache->name[cache_id],
data_size, cache_id);
/* Copy data to the buffer */
- dri_bo_subdata(bo, 0, data_size, data);
+ cache->sws->bo_subdata(bo, 0, data_size, data);
update_cache_last(cache, cache_id, bo);
reloc_bufs, nr_reloc_bufs);
if (item) {
update_cache_last(cache, cache_id, item->bo);
- brw->sws->bo_reference(item->bo);
+ cache->sws->bo_reference(item->bo);
return item->bo;
}
struct brw_cache *cache = &brw->cache;
cache->brw = brw;
+ cache->sws = brw->sws;
cache->size = 7;
cache->n_items = 0;
cache->items = (struct brw_cache_item **)
- _mesa_calloc(cache->size * sizeof(struct brw_cache_item));
+ CALLOC(cache->size, sizeof(struct brw_cache_item));
brw_init_cache_id(cache,
"CC_VP",
cache->size = 7;
cache->n_items = 0;
cache->items = (struct brw_cache_item **)
- _mesa_calloc(cache->size * sizeof(struct brw_cache_item));
+ CALLOC(cache->size, sizeof(struct brw_cache_item));
brw_init_cache_id(cache,
"SS_SURFACE",
struct brw_cache_item *c, *next;
GLuint i;
- if (INTEL_DEBUG & DEBUG_STATE)
- _mesa_printf("%s\n", __FUNCTION__);
+ if (BRW_DEBUG & DEBUG_STATE)
+ debug_printf("%s\n", __FUNCTION__);
for (i = 0; i < cache->size; i++) {
for (c = cache->items[i]; c; c = next) {
cache->n_items = 0;
if (brw->curbe.last_buf) {
- _mesa_free(brw->curbe.last_buf);
+ FREE(brw->curbe.last_buf);
brw->curbe.last_buf = NULL;
}
struct brw_cache_item **prev;
GLuint i;
- if (INTEL_DEBUG & DEBUG_STATE)
- _mesa_printf("%s\n", __FUNCTION__);
+ if (BRW_DEBUG & DEBUG_STATE)
+ debug_printf("%s\n", __FUNCTION__);
for (i = 0; i < cache->size; i++) {
for (prev = &cache->items[i]; *prev;) {
*prev = c->next;
for (j = 0; j < c->nr_reloc_bufs; j++)
- brw->sws->bo_unreference(c->reloc_bufs[j]);
- brw->sws->bo_unreference(c->bo);
+ cache->sws->bo_unreference(c->reloc_bufs[j]);
+ cache->sws->bo_unreference(c->bo);
free((void *)c->key);
free(c);
cache->n_items--;
void
brw_state_cache_check_size(struct brw_context *brw)
{
- if (INTEL_DEBUG & DEBUG_STATE)
- _mesa_printf("%s (n_items=%d)\n", __FUNCTION__, brw->cache.n_items);
+ if (BRW_DEBUG & DEBUG_STATE)
+ debug_printf("%s (n_items=%d)\n", __FUNCTION__, brw->cache.n_items);
/* un-tuned guess. We've got around 20 state objects for a total of around
* 32k, so 1000 of them is around 1.5MB.
{
GLuint i;
- if (INTEL_DEBUG & DEBUG_STATE)
- _mesa_printf("%s\n", __FUNCTION__);
+ if (BRW_DEBUG & DEBUG_STATE)
+ debug_printf("%s\n", __FUNCTION__);
brw_clear_cache(brw, cache);
for (i = 0; i < BRW_MAX_CACHE; i++) {
if (bit_map[i].bit == 0)
return;
- fprintf(stderr, "0x%08x: %12d (%s)\n",
+ debug_printf("0x%08x: %12d (%s)\n",
bit_map[i].bit, bit_map[i].count, bit_map[i].name);
}
}
+void
+brw_update_dirty_counts( unsigned mesa,
+ unsigned brw,
+ unsigned cache )
+{
+ static int dirty_count = 0;
+
+ brw_update_dirty_count(mesa_bits, mesa);
+ brw_update_dirty_count(brw_bits, brw);
+ brw_update_dirty_count(cache_bits, cache);
+ if (dirty_count++ % 1000 == 0) {
+ brw_print_dirty_count(mesa_bits, mesa);
+ brw_print_dirty_count(brw_bits, brw);
+ brw_print_dirty_count(cache_bits, cache);
+ debug_printf("\n");
+ }
+}
#include "brw_context.h"
#include "brw_state.h"
#include "brw_defines.h"
+#include "brw_winsys.h"
/**
* Prints out a header, the contents, and the message associated with
{
va_list va;
- fprintf(stderr, "%8s: 0x%08x: 0x%08x: ",
- name, hw_offset + index * 4, ((uint32_t *)data)[index]);
+ debug_printf("%8s: 0x%08x: 0x%08x: ",
+ name, hw_offset + index * 4, ((uint32_t *)data)[index]);
va_start(va, fmt);
- vfprintf(stderr, fmt, va);
+ debug_vprintf(fmt, va);
va_end(va);
}
/** Generic, undecoded state buffer debug printout */
static void
-state_struct_out(const char *name, struct brw_winsys_buffer *buffer, unsigned int state_size)
+state_struct_out(struct brw_winsys_screen *sws,
+ const char *name,
+ struct brw_winsys_buffer *buffer,
+ unsigned int state_size)
{
int i;
+ void *data;
if (buffer == NULL)
return;
- dri_bo_map(buffer, GL_FALSE);
+ data = sws->bo_map(buffer, GL_FALSE);
for (i = 0; i < state_size / 4; i++) {
- state_out(name, buffer->virtual, buffer->offset, i,
+ state_out(name, data, buffer->offset, i,
"dword %d\n", i);
}
- dri_bo_unmap(buffer);
+ sws->bo_unmap(buffer);
}
static const char *
char name[20];
if (surf_bo == NULL) {
- fprintf(stderr, " WM SS%d: NULL\n", i);
+ debug_printf(" WM SS%d: NULL\n", i);
continue;
}
- dri_bo_map(surf_bo, GL_FALSE);
+ surf = (struct brw_surface_state *)brw->sws->bo_map(surf_bo, GL_FALSE);
surfoff = surf_bo->offset;
- surf = (struct brw_surface_state *)(surf_bo->virtual);
sprintf(name, "WM SS%d", i);
state_out(name, surf, surfoff, 0, "%s %s\n",
state_out(name, surf, surfoff, 5, "x,y offset: %d,%d\n",
surf->ss5.x_offset, surf->ss5.y_offset);
- dri_bo_unmap(surf_bo);
+ brw->sws->bo_unmap(surf_bo);
}
}
if (brw->sf.vp_bo == NULL)
return;
- dri_bo_map(brw->sf.vp_bo, GL_FALSE);
-
- vp = brw->sf.vp_bo->virtual;
+ vp = (struct brw_sf_viewport *)brw->sws->bo_map(brw->sf.vp_bo, GL_FALSE);
vp_off = brw->sf.vp_bo->offset;
state_out(name, vp, vp_off, 0, "m00 = %f\n", vp->viewport.m00);
state_out(name, vp, vp_off, 7, "bottom right = %d,%d\n",
vp->scissor.xmax, vp->scissor.ymax);
- dri_bo_unmap(brw->sf.vp_bo);
+ brw->sws->bo_unmap(brw->sf.vp_bo);
}
-static void brw_debug_prog(const char *name, struct brw_winsys_buffer *prog)
+static void brw_debug_prog(struct brw_winsys_screen *sws,
+ const char *name,
+ struct brw_winsys_buffer *prog)
{
unsigned int i;
uint32_t *data;
if (prog == NULL)
return;
- dri_bo_map(prog, GL_FALSE);
-
- data = prog->virtual;
+ data = (uint32_t *)sws->bo_map(prog, GL_FALSE);
for (i = 0; i < prog->size / 4 / 4; i++) {
- fprintf(stderr, "%8s: 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
+ debug_printf("%8s: 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
name, (unsigned int)prog->offset + i * 4 * 4,
data[i * 4], data[i * 4 + 1], data[i * 4 + 2], data[i * 4 + 3]);
/* Stop at the end of the program. It'd be nice to keep track of the actual
break;
}
- dri_bo_unmap(prog);
+ sws->bo_unmap(prog);
}
*/
void brw_debug_batch(struct brw_context *brw)
{
- state_struct_out("WM bind", brw->wm.bind_bo, 4 * brw->wm.nr_surfaces);
+ struct brw_winsys_screen *sws = brw->sws;
+
+ state_struct_out(sws, "WM bind", brw->wm.bind_bo, 4 * brw->wm.nr_surfaces);
dump_wm_surface_state(brw);
- state_struct_out("VS", brw->vs.state_bo, sizeof(struct brw_vs_unit_state));
- brw_debug_prog("VS prog", brw->vs.prog_bo);
+ state_struct_out(sws, "VS", brw->vs.state_bo, sizeof(struct brw_vs_unit_state));
+ brw_debug_prog(sws, "VS prog", brw->vs.prog_bo);
- state_struct_out("GS", brw->gs.state_bo, sizeof(struct brw_gs_unit_state));
- brw_debug_prog("GS prog", brw->gs.prog_bo);
+ state_struct_out(sws, "GS", brw->gs.state_bo, sizeof(struct brw_gs_unit_state));
+ brw_debug_prog(sws, "GS prog", brw->gs.prog_bo);
- state_struct_out("SF", brw->sf.state_bo, sizeof(struct brw_sf_unit_state));
+ state_struct_out(sws, "SF", brw->sf.state_bo, sizeof(struct brw_sf_unit_state));
dump_sf_viewport_state(brw);
- brw_debug_prog("SF prog", brw->sf.prog_bo);
+ brw_debug_prog(sws, "SF prog", brw->sf.prog_bo);
- state_struct_out("WM", brw->wm.state_bo, sizeof(struct brw_wm_unit_state));
- brw_debug_prog("WM prog", brw->wm.prog_bo);
+ state_struct_out(sws, "WM", brw->wm.state_bo, sizeof(struct brw_wm_unit_state));
+ brw_debug_prog(sws, "WM prog", brw->wm.prog_bo);
}
#include "brw_context.h"
#include "brw_state.h"
#include "brw_batchbuffer.h"
+#include "brw_debug.h"
/* This is used to initialize brw->state.atoms[]. We could use this
* list directly except for a single atom, brw_constant_buffer, which
&brw_blend_constant_color,
&brw_depthbuffer,
-
&brw_polygon_stipple,
- &brw_polygon_stipple_offset,
-
&brw_line_stipple,
- &brw_aa_line_parameters,
&brw_psp_urb_cbs,
{
struct brw_state_flags *state = &brw->state.dirty;
GLuint i;
+ int ret;
brw_clear_validated_bos(brw);
- brw_add_validated_bo(brw, intel->batch->buf);
+ brw_add_validated_bo(brw, brw->batch->buf);
- if (brw->emit_state_always) {
+ if (brw->flags.always_emit_state) {
state->mesa |= ~0;
state->brw |= ~0;
state->cache |= ~0;
* If this fails, we can experience GPU lock-ups.
*/
{
- const struct brw_fragment_program *fp = brw->fragment_program;
+ const struct brw_fragment_shader *fp = brw->curr.fragment_shader;
if (fp) {
- assert(fp->info.max_sampler <= brw->nr_samplers &&
- fp->info.max_texture <= brw->nr_textures);
+ assert(fp->info.file_max[TGSI_FILE_SAMPLER] < brw->curr.num_samplers &&
+ fp->info.texture_max < brw->curr.num_textures);
}
}
enum pipe_error brw_upload_state(struct brw_context *brw)
{
struct brw_state_flags *state = &brw->state.dirty;
+ int ret;
int i;
- static int dirty_count = 0;
brw_clear_validated_bos(brw);
- if (INTEL_DEBUG) {
+ if (BRW_DEBUG) {
/* Debug version which enforces various sanity checks on the
* state flags which are generated and checked to help ensure
* state atoms are ordered correctly in the list.
*/
struct brw_state_flags examined, prev;
- _mesa_memset(&examined, 0, sizeof(examined));
+ memset(&examined, 0, sizeof(examined));
prev = *state;
for (i = 0; i < Elements(atoms); i++) {
}
}
- if (INTEL_DEBUG & DEBUG_STATE) {
- brw_update_dirty_count(mesa_bits, state->mesa);
- brw_update_dirty_count(brw_bits, state->brw);
- brw_update_dirty_count(cache_bits, state->cache);
- if (dirty_count++ % 1000 == 0) {
- brw_print_dirty_count(mesa_bits, state->mesa);
- brw_print_dirty_count(brw_bits, state->brw);
- brw_print_dirty_count(cache_bits, state->cache);
- debug_printf("\n");
- }
+ if (BRW_DEBUG & DEBUG_STATE) {
+ brw_update_dirty_counts( state->mesa,
+ state->brw,
+ state->cache );
}
/* Clear dirty flags:
*/
memset(state, 0, sizeof(*state));
+ return 0;
}
+++ /dev/null
-/*
- Copyright (C) Intel Corp. 2006. All Rights Reserved.
- Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
- develop this 3D driver.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice (including the
- next paragraph) shall be included in all copies or substantial
- portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
- **********************************************************************/
- /*
- * Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
- */
-
-
-#include "brw_context.h"
-
-/**
- * Finalizes all textures, completing any rendering that needs to be done
- * to prepare them.
- */
-void brw_validate_textures( struct brw_context *brw )
-{
- int i;
-
- for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
- struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
-
- if (texUnit->_ReallyEnabled) {
- intel_finalize_mipmap_tree(intel, i);
- }
- }
-}
+++ /dev/null
-/*
- Copyright (C) Intel Corp. 2006. All Rights Reserved.
- Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
- develop this 3D driver.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice (including the
- next paragraph) shall be included in all copies or substantial
- portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
- **********************************************************************/
- /*
- * Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
- */
-
-/* Code to layout images in a mipmap tree for i965.
- */
-
-#include "brw_tex_layout.h"
-
-#define FILE_DEBUG_FLAG DEBUG_MIPTREE
-
-GLboolean brw_miptree_layout(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- uint32_t tiling)
-{
- /* XXX: these vary depending on image format: */
- /* GLint align_w = 4; */
-
- switch (mt->target) {
- case GL_TEXTURE_CUBE_MAP:
- if (IS_IGDNG(brw->brw_screen->pci_id)) {
- GLuint align_h = 2, align_w = 4;
- GLuint level;
- GLuint x = 0;
- GLuint y = 0;
- GLuint width = mt->width0;
- GLuint height = mt->height0;
- GLuint qpitch = 0;
- GLuint y_pitch = 0;
-
- mt->pitch = mt->width0;
- intel_get_texture_alignment_unit(mt->internal_format, &align_w, &align_h);
- y_pitch = ALIGN(height, align_h);
-
- if (mt->compressed) {
- mt->pitch = ALIGN(mt->width0, align_w);
- }
-
- if (mt->last_level != 0) {
- GLuint mip1_width;
-
- if (mt->compressed) {
- mip1_width = ALIGN(minify(mt->width0), align_w)
- + ALIGN(minify(minify(mt->width0)), align_w);
- } else {
- mip1_width = ALIGN(minify(mt->width0), align_w)
- + minify(minify(mt->width0));
- }
-
- if (mip1_width > mt->pitch) {
- mt->pitch = mip1_width;
- }
- }
-
- mt->pitch = intel_miptree_pitch_align(intel, mt, tiling, mt->pitch);
-
- if (mt->compressed) {
- qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) / 4 * mt->pitch * mt->cpp;
- mt->total_height = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) / 4 * 6;
- } else {
- qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) * mt->pitch * mt->cpp;
- mt->total_height = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) * 6;
- }
-
- for (level = 0; level <= mt->last_level; level++) {
- GLuint img_height;
- GLuint nr_images = 6;
- GLuint q = 0;
-
- intel_miptree_set_level_info(mt, level, nr_images, x, y, width,
- height, 1);
-
- for (q = 0; q < nr_images; q++)
- intel_miptree_set_image_offset_ex(mt, level, q, x, y, q * qpitch);
-
- if (mt->compressed)
- img_height = MAX2(1, height/4);
- else
- img_height = ALIGN(height, align_h);
-
- if (level == 1) {
- x += ALIGN(width, align_w);
- }
- else {
- y += img_height;
- }
-
- width = minify(width);
- height = minify(height);
- }
-
- break;
- }
-
- case GL_TEXTURE_3D: {
- GLuint width = mt->width0;
- GLuint height = mt->height0;
- GLuint depth = mt->depth0;
- GLuint pack_x_pitch, pack_x_nr;
- GLuint pack_y_pitch;
- GLuint level;
- GLuint align_h = 2;
- GLuint align_w = 4;
-
- mt->total_height = 0;
- intel_get_texture_alignment_unit(mt->internal_format, &align_w, &align_h);
-
- if (mt->compressed) {
- mt->pitch = ALIGN(width, align_w);
- pack_y_pitch = (height + 3) / 4;
- } else {
- mt->pitch = intel_miptree_pitch_align (intel, mt, tiling, mt->width0);
- pack_y_pitch = ALIGN(mt->height0, align_h);
- }
-
- pack_x_pitch = width;
- pack_x_nr = 1;
-
- for (level = 0 ; level <= mt->last_level ; level++) {
- GLuint nr_images = mt->target == GL_TEXTURE_3D ? depth : 6;
- GLint x = 0;
- GLint y = 0;
- GLint q, j;
-
- intel_miptree_set_level_info(mt, level, nr_images,
- 0, mt->total_height,
- width, height, depth);
-
- for (q = 0; q < nr_images;) {
- for (j = 0; j < pack_x_nr && q < nr_images; j++, q++) {
- intel_miptree_set_image_offset(mt, level, q, x, y);
- x += pack_x_pitch;
- }
-
- x = 0;
- y += pack_y_pitch;
- }
-
-
- mt->total_height += y;
- width = minify(width);
- height = minify(height);
- depth = minify(depth);
-
- if (mt->compressed) {
- pack_y_pitch = (height + 3) / 4;
-
- if (pack_x_pitch > ALIGN(width, align_w)) {
- pack_x_pitch = ALIGN(width, align_w);
- pack_x_nr <<= 1;
- }
- } else {
- if (pack_x_pitch > 4) {
- pack_x_pitch >>= 1;
- pack_x_nr <<= 1;
- assert(pack_x_pitch * pack_x_nr <= mt->pitch);
- }
-
- if (pack_y_pitch > 2) {
- pack_y_pitch >>= 1;
- pack_y_pitch = ALIGN(pack_y_pitch, align_h);
- }
- }
-
- }
- /* The 965's sampler lays cachelines out according to how accesses
- * in the texture surfaces run, so they may be "vertical" through
- * memory. As a result, the docs say in Surface Padding Requirements:
- * Sampling Engine Surfaces that two extra rows of padding are required.
- * We don't know of similar requirements for pre-965, but given that
- * those docs are silent on padding requirements in general, let's play
- * it safe.
- */
- if (mt->target == GL_TEXTURE_CUBE_MAP)
- mt->total_height += 2;
- break;
- }
-
- default:
- i945_miptree_layout_2d(intel, mt, tiling);
- break;
- }
- DBG("%s: %dx%dx%d - sz 0x%x\n", __FUNCTION__,
- mt->pitch,
- mt->total_height,
- mt->cpp,
- mt->pitch * mt->total_height * mt->cpp );
-
- return GL_TRUE;
-}
-
* entries and the values for minimum nr of entries
* provided above.
*/
- _mesa_printf("couldn't calculate URB layout!\n");
+ debug_printf("couldn't calculate URB layout!\n");
exit(1);
}
- if (INTEL_DEBUG & (DEBUG_URB|DEBUG_FALLBACKS))
- _mesa_printf("URB CONSTRAINED\n");
+ if (BRW_DEBUG & (DEBUG_URB|DEBUG_FALLBACKS))
+ debug_printf("URB CONSTRAINED\n");
}
done:
- if (INTEL_DEBUG & DEBUG_URB)
- _mesa_printf("URB fence: %d ..VS.. %d ..GS.. %d ..CLP.. %d ..SF.. %d ..CS.. %d\n",
+ if (BRW_DEBUG & DEBUG_URB)
+ debug_printf("URB fence: %d ..VS.. %d ..GS.. %d ..CLP.. %d ..SF.. %d ..CS.. %d\n",
brw->urb.vs_start,
brw->urb.gs_start,
brw->urb.clip_start,
struct brw_reg r0;
struct brw_reg r1;
- struct brw_reg regs[PROGRAM_ADDRESS+1][128];
+ struct brw_reg regs[TGSI_FILE_COUNT][128];
struct brw_reg tmp;
struct brw_reg stack;
c->prog_data.total_grf = reg;
- if (INTEL_DEBUG & DEBUG_VS) {
- _mesa_printf("%s NumAddrRegs %d\n", __FUNCTION__, c->vp->program.Base.NumAddressRegs);
- _mesa_printf("%s NumTemps %d\n", __FUNCTION__, c->vp->program.Base.NumTemporaries);
- _mesa_printf("%s reg = %d\n", __FUNCTION__, reg);
+ if (BRW_DEBUG & DEBUG_VS) {
+ debug_printf("%s NumAddrRegs %d\n", __FUNCTION__, c->vp->program.Base.NumAddressRegs);
+ debug_printf("%s NumTemps %d\n", __FUNCTION__, c->vp->program.Base.NumTemporaries);
+ debug_printf("%s reg = %d\n", __FUNCTION__, reg);
}
}
GLuint index;
GLuint file;
- if (INTEL_DEBUG & DEBUG_VS) {
- _mesa_printf("vs-mesa:\n");
+ if (BRW_DEBUG & DEBUG_VS) {
+ debug_printf("vs-mesa:\n");
_mesa_print_program(&c->vp->program.Base);
- _mesa_printf("\n");
+ debug_printf("\n");
}
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
post_vs_emit(c, end_inst, last_inst);
- if (INTEL_DEBUG & DEBUG_VS) {
+ if (BRW_DEBUG & DEBUG_VS) {
int i;
- _mesa_printf("vs-native:\n");
+ debug_printf("vs-native:\n");
for (i = 0; i < p->nr_insn; i++)
brw_disasm(stderr, &p->store[i]);
- _mesa_printf("\n");
+ debug_printf("\n");
}
}
vs.thread4.max_threads = CLAMP(key->nr_urb_entries / 2,
1, chipset_max_threads) - 1;
- if (INTEL_DEBUG & DEBUG_SINGLE_THREAD)
+ if (BRW_DEBUG & DEBUG_SINGLE_THREAD)
vs.thread4.max_threads = 0;
/* No samplers for ARB_vp programs:
*/
vs.vs5.sampler_count = 0;
- if (INTEL_DEBUG & DEBUG_STATS)
+ if (BRW_DEBUG & DEBUG_STATS)
vs.thread4.stats_enable = 1;
/* Vertex program always enabled:
BRW_BUFFER_TYPE_SHADER_CONSTANTS,
BRW_BUFFER_TYPE_WM_SCRATCH,
BRW_BUFFER_TYPE_BATCH,
+ BRW_BUFFER_TYPE_STATE_CACHE,
};
unsigned offset,
struct brw_winsys_buffer *b2);
- void (*bo_subdata)(struct brw_winsys_buffer *dst,
+ void (*bo_subdata)(struct brw_winsys_buffer *buffer,
size_t offset,
size_t size,
const void *data);
+ boolean (*bo_is_busy)(struct brw_winsys_buffer *buffer);
+ boolean (*bo_references)(struct brw_winsys_buffer *a,
+ struct brw_winsys_buffer *b);
+
/* XXX: couldn't this be handled by returning true/false on
* bo_emit_reloc?
*/
/**
* Map a buffer.
*/
- void *(*buffer_map)(struct brw_winsys *iws,
- struct brw_winsys_buffer *buffer,
- boolean write);
+ void *(*bo_map)(struct brw_winsys_buffer *buffer,
+ boolean write);
/**
* Unmap a buffer.
*/
- void (*buffer_unmap)(struct brw_winsys *iws,
- struct brw_winsys_buffer *buffer);
-
- void (*buffer_destroy)(struct brw_winsys *iws,
- struct brw_winsys_buffer *buffer);
+ void (*bo_unmap)(struct brw_winsys_buffer *buffer);
/*@}*/
brw_wm_non_glsl_emit(brw, c);
}
- if (INTEL_DEBUG & DEBUG_WM)
- fprintf(stderr, "\n");
+ if (BRW_DEBUG & DEBUG_WM)
+ debug_printf("\n");
/* get the program
*/
#ifndef BRW_WM_H
#define BRW_WM_H
+#include "tgsi/tgsi_ureg.h"
#include "brw_context.h"
#include "brw_eu.h"
#define AA_ALWAYS 2
struct brw_wm_prog_key {
+ unsigned proj_attrib_mask; /**< one bit per fragment program attribute */
+ unsigned linear_attrib_mask:1; /**< linear interpolation vs perspective interp */
+
GLuint source_depth_reg:3;
GLuint aa_dest_stencil_reg:3;
GLuint dest_depth_reg:3;
GLuint nr_depth_regs:3;
- GLuint computes_depth:1; /* could be derived from program string */
+ GLuint computes_depth:1;
GLuint source_depth_to_render_target:1;
GLuint flat_shade:1;
- GLuint linear_color:1; /**< linear interpolation vs perspective interp */
GLuint runtime_check_aads_emit:1;
-
- GLbitfield proj_attrib_mask; /**< one bit per fragment program attribute */
+
GLuint shadowtex_mask:16;
GLuint yuvtex_mask:16;
GLuint yuvtex_swap_mask:16; /* UV swaped */
GLuint tex_swizzles[BRW_MAX_TEX_UNIT];
GLuint program_string_id:32;
- GLuint drawable_height;
+
GLuint vp_nr_outputs_written;
};
};
-#define BRW_WM_MAX_INSN (MAX_NV_FRAGMENT_PROGRAM_INSTRUCTIONS*3 + FRAG_ATTRIB_MAX + 3)
+#define BRW_WM_MAX_INSN 2048
#define BRW_WM_MAX_GRF 128 /* hardware limit */
#define BRW_WM_MAX_VREG (BRW_WM_MAX_INSN * 4)
#define BRW_WM_MAX_REF (BRW_WM_MAX_INSN * 12)
#define BRW_WM_MAX_SUBROUTINE 16
+struct ureg_instruction {
+ unsigned opcode:8;
+ unsigned tex_target:3;
+ struct ureg_dst dst;
+ struct ureg_src src[3];
+};
+
/* New opcodes to track internal operations required for WM unit.
* These are added early so that the registers used can be tracked,
* freed and reused like those of other instructions.
*/
+#define MAX_OPCODE TGSI_OPCODE_LAST
#define WM_PIXELXY (MAX_OPCODE)
#define WM_DELTAXY (MAX_OPCODE + 1)
#define WM_PIXELW (MAX_OPCODE + 2)
#define WM_FRONTFACING (MAX_OPCODE + 8)
#define MAX_WM_OPCODE (MAX_OPCODE + 9)
-#define PROGRAM_PAYLOAD (PROGRAM_FILE_MAX)
+#define PROGRAM_PAYLOAD (TGSI_FILE_COUNT)
#define PAYLOAD_DEPTH (FRAG_ATTRIB_MAX)
struct brw_wm_compile {
* simplifying and adding instructions for interpolation and
* framebuffer writes.
*/
- struct prog_instruction prog_instructions[BRW_WM_MAX_INSN];
+ struct ureg_instruction prog_instructions[BRW_WM_MAX_INSN];
GLuint nr_fp_insns;
GLuint fp_temp;
GLuint fp_interp_emitted;
GLuint fp_fragcolor_emitted;
- struct prog_src_register pixel_xy;
- struct prog_src_register delta_xy;
- struct prog_src_register pixel_w;
+ struct ureg_src pixel_xy;
+ struct ureg_src delta_xy;
+ struct ureg_src pixel_w;
struct brw_wm_value vreg[BRW_WM_MAX_VREG];
struct {
struct brw_wm_value depth[4]; /* includes r0/r1 */
- struct brw_wm_value input_interp[FRAG_ATTRIB_MAX];
+ struct brw_wm_value input_interp[PIPE_MAX_SHADER_INPUTS];
} payload;
GLboolean ps_uses_depth,
struct brw_wm_prog_key *key );
-GLboolean brw_wm_is_glsl(const struct gl_fragment_program *fp);
+//GLboolean brw_wm_is_glsl(const struct gl_fragment_program *fp);
void brw_wm_glsl_emit(struct brw_context *brw, struct brw_wm_compile *c);
void emit_ddxy(struct brw_compile *p,
if (c->state >= PASS2_DONE)
brw_print_reg(value->hw_reg);
else if( value == &c->undef_value )
- _mesa_printf("undef");
+ debug_printf("undef");
else if( value - c->vreg >= 0 &&
value - c->vreg < BRW_WM_MAX_VREG)
- _mesa_printf("r%d", value - c->vreg);
+ debug_printf("r%d", value - c->vreg);
else if (value - c->creg >= 0 &&
value - c->creg < BRW_WM_MAX_PARAM)
- _mesa_printf("c%d", value - c->creg);
+ debug_printf("c%d", value - c->creg);
else if (value - c->payload.input_interp >= 0 &&
value - c->payload.input_interp < FRAG_ATTRIB_MAX)
- _mesa_printf("i%d", value - c->payload.input_interp);
+ debug_printf("i%d", value - c->payload.input_interp);
else if (value - c->payload.depth >= 0 &&
value - c->payload.depth < FRAG_ATTRIB_MAX)
- _mesa_printf("d%d", value - c->payload.depth);
+ debug_printf("d%d", value - c->payload.depth);
else
- _mesa_printf("?");
+ debug_printf("?");
}
void brw_wm_print_ref( struct brw_wm_compile *c,
struct brw_reg hw_reg = ref->hw_reg;
if (ref->unspill_reg)
- _mesa_printf("UNSPILL(%x)/", ref->value->spill_slot);
+ debug_printf("UNSPILL(%x)/", ref->value->spill_slot);
if (c->state >= PASS2_DONE)
brw_print_reg(ref->hw_reg);
else {
- _mesa_printf("%s", hw_reg.negate ? "-" : "");
- _mesa_printf("%s", hw_reg.abs ? "abs/" : "");
+ debug_printf("%s", hw_reg.negate ? "-" : "");
+ debug_printf("%s", hw_reg.abs ? "abs/" : "");
brw_wm_print_value(c, ref->value);
if ((hw_reg.nr&1) || hw_reg.subnr) {
- _mesa_printf("->%d.%d", (hw_reg.nr&1), hw_reg.subnr);
+ debug_printf("->%d.%d", (hw_reg.nr&1), hw_reg.subnr);
}
}
}
GLuint i, arg;
GLuint nr_args = brw_wm_nr_args(inst->opcode);
- _mesa_printf("[");
+ debug_printf("[");
for (i = 0; i < 4; i++) {
if (inst->dst[i]) {
brw_wm_print_value(c, inst->dst[i]);
if (inst->dst[i]->spill_slot)
- _mesa_printf("/SPILL(%x)",inst->dst[i]->spill_slot);
+ debug_printf("/SPILL(%x)",inst->dst[i]->spill_slot);
}
else
- _mesa_printf("#");
+ debug_printf("#");
if (i < 3)
- _mesa_printf(",");
+ debug_printf(",");
}
- _mesa_printf("]");
+ debug_printf("]");
if (inst->writemask != BRW_WRITEMASK_XYZW)
- _mesa_printf(".%s%s%s%s",
+ debug_printf(".%s%s%s%s",
GET_BIT(inst->writemask, 0) ? "x" : "",
GET_BIT(inst->writemask, 1) ? "y" : "",
GET_BIT(inst->writemask, 2) ? "z" : "",
switch (inst->opcode) {
case WM_PIXELXY:
- _mesa_printf(" = PIXELXY");
+ debug_printf(" = PIXELXY");
break;
case WM_DELTAXY:
- _mesa_printf(" = DELTAXY");
+ debug_printf(" = DELTAXY");
break;
case WM_PIXELW:
- _mesa_printf(" = PIXELW");
+ debug_printf(" = PIXELW");
break;
case WM_WPOSXY:
- _mesa_printf(" = WPOSXY");
+ debug_printf(" = WPOSXY");
break;
case WM_PINTERP:
- _mesa_printf(" = PINTERP");
+ debug_printf(" = PINTERP");
break;
case WM_LINTERP:
- _mesa_printf(" = LINTERP");
+ debug_printf(" = LINTERP");
break;
case WM_CINTERP:
- _mesa_printf(" = CINTERP");
+ debug_printf(" = CINTERP");
break;
case WM_FB_WRITE:
- _mesa_printf(" = FB_WRITE");
+ debug_printf(" = FB_WRITE");
break;
case WM_FRONTFACING:
- _mesa_printf(" = FRONTFACING");
+ debug_printf(" = FRONTFACING");
break;
default:
- _mesa_printf(" = %s", _mesa_opcode_string(inst->opcode));
+ debug_printf(" = %s", _mesa_opcode_string(inst->opcode));
break;
}
if (inst->saturate)
- _mesa_printf("_SAT");
+ debug_printf("_SAT");
for (arg = 0; arg < nr_args; arg++) {
- _mesa_printf(" [");
+ debug_printf(" [");
for (i = 0; i < 4; i++) {
if (inst->src[arg][i]) {
brw_wm_print_ref(c, inst->src[arg][i]);
}
else
- _mesa_printf("%%");
+ debug_printf("%%");
if (i < 3)
- _mesa_printf(",");
+ debug_printf(",");
else
- _mesa_printf("]");
+ debug_printf("]");
}
}
- _mesa_printf("\n");
+ debug_printf("\n");
}
void brw_wm_print_program( struct brw_wm_compile *c,
{
GLuint insn;
- _mesa_printf("%s:\n", stage);
+ debug_printf("%s:\n", stage);
for (insn = 0; insn < c->nr_insns; insn++)
brw_wm_print_insn(c, &c->instruction[insn]);
- _mesa_printf("\n");
+ debug_printf("\n");
}
break;
default:
- _mesa_printf("Unsupported opcode %i (%s) in fragment shader\n",
+ debug_printf("Unsupported opcode %i (%s) in fragment shader\n",
inst->opcode, inst->opcode < MAX_OPCODE ?
_mesa_opcode_string(inst->opcode) :
"unknown");
inst->dst[i]->spill_slot);
}
- if (INTEL_DEBUG & DEBUG_WM) {
+ if (BRW_DEBUG & DEBUG_WM) {
int i;
- _mesa_printf("wm-native:\n");
+ debug_printf("wm-native:\n");
for (i = 0; i < p->nr_insn; i++)
brw_disasm(stderr, &p->store[i]);
- _mesa_printf("\n");
+ debug_printf("\n");
}
}
int bit = _mesa_ffs( ~c->fp_temp );
if (!bit) {
- _mesa_printf("%s: out of temporaries\n", __FILE__);
+ debug_printf("%s: out of temporaries\n", __FILE__);
exit(1);
}
{
GLuint i;
for (i = 0; i < nr; i++, insn++) {
- _mesa_printf("%3d: ", i);
+ debug_printf("%3d: ", i);
if (insn->Opcode < MAX_OPCODE)
_mesa_print_instruction(insn);
else if (insn->Opcode < MAX_WM_OPCODE) {
3);
}
else
- _mesa_printf("965 Opcode %d\n", insn->Opcode);
+ debug_printf("965 Opcode %d\n", insn->Opcode);
}
}
struct brw_fragment_program *fp = c->fp;
GLuint insn;
- if (INTEL_DEBUG & DEBUG_WM) {
- _mesa_printf("pre-fp:\n");
+ if (BRW_DEBUG & DEBUG_WM) {
+ debug_printf("pre-fp:\n");
_mesa_print_program(&fp->program.Base);
- _mesa_printf("\n");
+ debug_printf("\n");
}
c->pixel_xy = src_undef();
}
}
- if (INTEL_DEBUG & DEBUG_WM) {
- _mesa_printf("pass_fp:\n");
+ if (BRW_DEBUG & DEBUG_WM) {
+ debug_printf("pass_fp:\n");
print_insns( c->prog_instructions, c->nr_fp_insns );
- _mesa_printf("\n");
+ debug_printf("\n");
}
}
c->cur_inst = i;
#if 0
- _mesa_printf("Inst %d: ", i);
+ debug_printf("Inst %d: ", i);
_mesa_print_instruction(inst);
#endif
}
break;
default:
- _mesa_printf("unsupported IR in fragment shader %d\n",
+ debug_printf("unsupported IR in fragment shader %d\n",
inst->Opcode);
}
}
post_wm_emit(c);
- if (INTEL_DEBUG & DEBUG_WM) {
- _mesa_printf("wm-native:\n");
+ if (BRW_DEBUG & DEBUG_WM) {
+ debug_printf("wm-native:\n");
for (i = 0; i < p->nr_insn; i++)
brw_disasm(stderr, &p->store[i]);
- _mesa_printf("\n");
+ debug_printf("\n");
}
}
*/
void brw_wm_glsl_emit(struct brw_context *brw, struct brw_wm_compile *c)
{
- if (INTEL_DEBUG & DEBUG_WM) {
- _mesa_printf("brw_wm_glsl_emit:\n");
+ if (BRW_DEBUG & DEBUG_WM) {
+ debug_printf("brw_wm_glsl_emit:\n");
}
/* initial instruction translation/simplification */
/* actual code generation */
brw_wm_emit_glsl(brw, c);
- if (INTEL_DEBUG & DEBUG_WM) {
+ if (BRW_DEBUG & DEBUG_WM) {
brw_wm_print_program(c, "brw_wm_glsl_emit done");
}
GLuint i = c->prog_data.nr_params++;
if (i >= BRW_WM_MAX_PARAM) {
- _mesa_printf("%s: out of params\n", __FUNCTION__);
+ debug_printf("%s: out of params\n", __FUNCTION__);
c->prog_data.error = 1;
return NULL;
}
return c->imm_ref[i].ref;
}
else {
- _mesa_printf("%s: out of imm_refs\n", __FUNCTION__);
+ debug_printf("%s: out of imm_refs\n", __FUNCTION__);
c->prog_data.error = 1;
return NULL;
}
}
}
- if (INTEL_DEBUG & DEBUG_WM) {
+ if (BRW_DEBUG & DEBUG_WM) {
brw_wm_print_program(c, "pass0");
}
}
track_arg(c, inst, 2, read2);
}
- if (INTEL_DEBUG & DEBUG_WM) {
+ if (BRW_DEBUG & DEBUG_WM) {
brw_wm_print_program(c, "pass1");
}
}
}
}
- if (INTEL_DEBUG & DEBUG_WM) {
+ if (BRW_DEBUG & DEBUG_WM) {
brw_wm_print_program(c, "pass2");
}
c->state = PASS2_DONE;
- if (INTEL_DEBUG & DEBUG_WM) {
+ if (BRW_DEBUG & DEBUG_WM) {
brw_wm_print_program(c, "pass2/done");
}
}
}
-static struct brw_winsys_buffer *upload_default_color( struct brw_context *brw,
- const GLfloat *color )
+static struct brw_winsys_buffer *
+upload_default_color( struct brw_context *brw,
+ const GLfloat *color )
{
struct brw_sampler_default_color sdc;
{
_mesa_memset(sampler, 0, sizeof(*sampler));
- switch (key->minfilter) {
- case GL_NEAREST:
- sampler->ss0.min_filter = BRW_MAPFILTER_NEAREST;
- sampler->ss0.mip_filter = BRW_MIPFILTER_NONE;
- break;
- case GL_LINEAR:
- sampler->ss0.min_filter = BRW_MAPFILTER_LINEAR;
- sampler->ss0.mip_filter = BRW_MIPFILTER_NONE;
- break;
- case GL_NEAREST_MIPMAP_NEAREST:
- sampler->ss0.min_filter = BRW_MAPFILTER_NEAREST;
- sampler->ss0.mip_filter = BRW_MIPFILTER_NEAREST;
- break;
- case GL_LINEAR_MIPMAP_NEAREST:
- sampler->ss0.min_filter = BRW_MAPFILTER_LINEAR;
- sampler->ss0.mip_filter = BRW_MIPFILTER_NEAREST;
- break;
- case GL_NEAREST_MIPMAP_LINEAR:
- sampler->ss0.min_filter = BRW_MAPFILTER_NEAREST;
- sampler->ss0.mip_filter = BRW_MIPFILTER_LINEAR;
- break;
- case GL_LINEAR_MIPMAP_LINEAR:
- sampler->ss0.min_filter = BRW_MAPFILTER_LINEAR;
- sampler->ss0.mip_filter = BRW_MIPFILTER_LINEAR;
- break;
- default:
- break;
- }
-
- /* Set Anisotropy:
- */
- if (key->max_aniso > 1.0) {
- sampler->ss0.min_filter = BRW_MAPFILTER_ANISOTROPIC;
- sampler->ss0.mag_filter = BRW_MAPFILTER_ANISOTROPIC;
-
- if (key->max_aniso > 2.0) {
- sampler->ss3.max_aniso = MIN2((key->max_aniso - 2) / 2,
- BRW_ANISORATIO_16);
- }
- }
- else {
- switch (key->magfilter) {
- case GL_NEAREST:
- sampler->ss0.mag_filter = BRW_MAPFILTER_NEAREST;
- break;
- case GL_LINEAR:
- sampler->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
- break;
- default:
- break;
- }
- }
-
- sampler->ss1.r_wrap_mode = translate_wrap_mode(key->wrap_r);
- sampler->ss1.s_wrap_mode = translate_wrap_mode(key->wrap_s);
- sampler->ss1.t_wrap_mode = translate_wrap_mode(key->wrap_t);
-
/* Cube-maps on 965 and later must use the same wrap mode for all 3
* coordinate dimensions. Futher, only CUBE and CLAMP are valid.
*/
}
- /* Set shadow function:
- */
- if (key->comparemode == GL_COMPARE_R_TO_TEXTURE_ARB) {
- /* Shadowing is "enabled" by emitting a particular sampler
- * message (sample_c). So need to recompile WM program when
- * shadow comparison is enabled on each/any texture unit.
- */
- sampler->ss0.shadow_function =
- intel_translate_shadow_compare_func(key->comparefunc);
- }
-
- /* Set LOD bias:
- */
- sampler->ss0.lod_bias = S_FIXED(CLAMP(key->lod_bias, -16, 15), 6);
-
- sampler->ss0.lod_preclamp = 1; /* OpenGL mode */
- sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */
-
- /* Set BaseMipLevel, MaxLOD, MinLOD:
- *
- * XXX: I don't think that using firstLevel, lastLevel works,
- * because we always setup the surface state as if firstLevel ==
- * level zero. Probably have to subtract firstLevel from each of
- * these:
- */
- sampler->ss0.base_level = U_FIXED(0, 1);
- sampler->ss1.max_lod = U_FIXED(MIN2(MAX2(key->maxlod, 0), 13), 6);
- sampler->ss1.min_lod = U_FIXED(MIN2(MAX2(key->minlod, 0), 13), 6);
-
sampler->ss2.default_color_pointer = sdc_bo->offset >> 5; /* reloc */
}
brw_wm_sampler_populate_key(struct brw_context *brw,
struct wm_sampler_key *key)
{
- int unit;
+ int nr = MIN2(brw->curr.number_textures,
+ brw->curr.number_samplers);
+ int i;
memset(key, 0, sizeof(*key));
- for (unit = 0; unit < BRW_MAX_TEX_UNIT; unit++) {
- if (ctx->Texture.Unit[unit]._ReallyEnabled) {
- struct wm_sampler_entry *entry = &key->sampler[unit];
- struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
- struct gl_texture_object *texObj = texUnit->_Current;
- struct intel_texture_object *intelObj = intel_texture_object(texObj);
- struct gl_texture_image *firstImage =
- texObj->Image[0][intelObj->firstLevel];
-
- entry->tex_target = texObj->Target;
-
- entry->seamless_cube_map = (texObj->Target == GL_TEXTURE_CUBE_MAP)
- ? ctx->Texture.CubeMapSeamless : GL_FALSE;
-
- entry->wrap_r = texObj->WrapR;
- entry->wrap_s = texObj->WrapS;
- entry->wrap_t = texObj->WrapT;
-
- entry->maxlod = texObj->MaxLod;
- entry->minlod = texObj->MinLod;
- entry->lod_bias = texUnit->LodBias + texObj->LodBias;
- entry->max_aniso = texObj->MaxAnisotropy;
- entry->minfilter = texObj->MinFilter;
- entry->magfilter = texObj->MagFilter;
- entry->comparemode = texObj->CompareMode;
- entry->comparefunc = texObj->CompareFunc;
-
- brw->sws->bo_unreference(brw->wm.sdc_bo[unit]);
- if (firstImage->_BaseFormat == GL_DEPTH_COMPONENT) {
- float bordercolor[4] = {
- texObj->BorderColor[0],
- texObj->BorderColor[0],
- texObj->BorderColor[0],
- texObj->BorderColor[0]
- };
- /* GL specs that border color for depth textures is taken from the
- * R channel, while the hardware uses A. Spam R into all the
- * channels for safety.
- */
- brw->wm.sdc_bo[unit] = upload_default_color(brw, bordercolor);
- } else {
- brw->wm.sdc_bo[unit] = upload_default_color(brw,
- texObj->BorderColor);
- }
- key->sampler_count = unit + 1;
+ for (i = 0; i < nr; i++) {
+ const struct brw_texture *tex = brw->curr.texture[i];
+ const struct brw_sampler *sampler = brw->curr.sampler[i];
+ struct wm_sampler_entry *entry = &key->sampler[i];
+
+ entry->tex_target = texObj->Target;
+ entry->seamless_cube_map = FALSE; /* XXX: add this to gallium */
+ entry->ss0 = sampler->ss0;
+ entry->ss1 = sampler->ss1;
+ entry->ss3 = sampler->ss3;
+
+ brw->sws->bo_unreference(brw->wm.sdc_bo[i]);
+ if (firstImage->_BaseFormat == GL_DEPTH_COMPONENT) {
+ float bordercolor[4] = {
+ texObj->BorderColor[0],
+ texObj->BorderColor[0],
+ texObj->BorderColor[0],
+ texObj->BorderColor[0]
+ };
+ /* GL specs that border color for depth textures is taken from the
+ * R channel, while the hardware uses A. Spam R into all the
+ * channels for safety.
+ */
+ brw->wm.sdc_bo[i] = upload_default_color(brw, bordercolor);
+ } else {
+ brw->wm.sdc_bo[i] = upload_default_color(brw, texObj->BorderColor);
}
}
+
+ key->sampler_count = nr;
}
/* All samplers must be uploaded in a single contiguous array, which
const struct brw_tracked_state brw_wm_samplers = {
.dirty = {
- .mesa = _NEW_TEXTURE,
+ .mesa = PIPE_NEW_BOUND_TEXTURES | PIPE_NEW_SAMPLER,
.brw = 0,
.cache = 0
},
memset(key, 0, sizeof(*key));
- if (INTEL_DEBUG & DEBUG_SINGLE_THREAD)
+ if (BRW_DEBUG & DEBUG_SINGLE_THREAD)
key->max_threads = 1;
else {
/* WM maximum threads is number of EUs times number of threads per EU. */
ASSERT(bfp->isGLSL == brw_wm_is_glsl(fp));
/* _NEW_QUERY */
- key->stats_wm = intel->stats_wm;
+ key->stats_wm = (brw->query.stats_wm != 0);
/* _NEW_LINE */
key->line_stipple = ctx->Line.StippleFlag;
wm.wm5.line_stipple = key->line_stipple;
- if (INTEL_DEBUG & DEBUG_STATS || key->stats_wm)
+ if (BRW_DEBUG & DEBUG_STATS || key->stats_wm)
wm.wm4.stats_enable = 1;
bo = brw_upload_cache(&brw->cache, BRW_WM_UNIT,
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