Get rid of sigBset too

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index 0d1937844cd8b66c0856d05e0e53f3f19c22564f..c742ef84d5aebebcf313592e1f8e3af7a7f359dc 100644 (file)
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -23,10 +23,6 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-template<class T> inline bool includes(const T &lhs, const T &rhs) {
-       return std::includes(lhs.begin(), lhs.end(), rhs.begin(), rhs.end());
-}
-#include <set>
 #include "passes/pmgen/xilinx_dsp_pm.h"
 
 void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 598276063c6dfdc49deb33b7373461efaa980bbe..d37792b29455b206d6927b47640c02c1d7044f3d 100644 (file)
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -1,24 +1,25 @@
 pattern xilinx_dsp
 
 state <SigBit> clock
-state <std::set<SigBit>> sigBset
-state <SigSpec> sigA sigC sigM sigP sigPused
+state <SigSpec> sigA sigB sigC sigM sigP sigPused
 state <IdString> ffMmuxAB postAddAB postAddMuxAB
 
 match dsp
        select dsp->type.in(\DSP48E1)
 endmatch
 
-code sigA sigBset
+code sigA sigB
        sigA = port(dsp, \A);
        int i;
        for (i = GetSize(sigA)-1; i > 0; i--)
                if (sigA[i] != sigA[i-1])
                        break;
        sigA.remove(i, GetSize(sigA)-i);
-       SigSpec B = port(dsp, \B);
-       B.remove_const();
-       sigBset = B.to_sigbit_set();
+       sigB = port(dsp, \B);
+       for (i = GetSize(sigB)-1; i > 0; i--)
+               if (sigB[i] != sigB[i-1])
+                       break;
+       sigB.remove(i, GetSize(sigB)-i);
 endcode
 
 code sigM
@@ -58,11 +59,12 @@ endcode
 
 match ffB
        if param(dsp, \BREG).as_int() == 0
-       if !sigBset.empty()
        select ffB->type.in($dff)
        // DSP48E1 does not support clock inversion
        select param(ffB, \CLK_POLARITY).as_bool()
-       filter includes(port(ffB, \Q).to_sigbit_set(), sigBset)
+       filter GetSize(port(ffB, \Q)) >= GetSize(sigB)
+       slice offset GetSize(port(ffB, \Q))
+       filter offset+GetSize(sigB) <= GetSize(port(ffB, \Q)) && port(ffB, \Q).extract(offset, GetSize(sigB)) == sigB
        optional
 endmatch