make fail-first cope with sv.cmp which uses CR[BF]

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 6f00233b42f990204bfe2fad4d91ecf93199f133..c4cb0c3978d589eeb58668b1244f65ab1236bbdb 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1855,13 +1855,14 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
         if self.is_svp64_mode:
             sv_mode = yield self.dec2.rm_dec.sv_mode
             is_cr = sv_mode == SVMode.CROP.value
-            ffirst_hit = (yield from self.check_ffirst(rc_en or is_cr, srcstep))
+            chk = rc_en or is_cr
+            ffirst_hit = (yield from self.check_ffirst(info, chk, srcstep))
 
         # any modified return results?
         yield from self.do_outregs_nia(asmop, ins_name, info, outs,
                                        carry_en, rc_en, ffirst_hit)
 
-    def check_ffirst(self, rc_en, srcstep):
+    def check_ffirst(self, info, rc_en, srcstep):
         """fail-first mode: checks a bit of Rc Vector, truncates VL
         """
         rm_mode = yield self.dec2.rm_dec.mode
@@ -1878,10 +1879,14 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
         if not rc_en or rm_mode != SVP64RMMode.FFIRST.value:
             return False
         # get the CR vevtor, do BO-test
-        regnum, is_vec = yield from get_pdecode_cr_out(self.dec2, "CR0")
+        crf = "CR0"
+        log("asmregs", info.asmregs[0], info.write_regs)
+        if 'CR' in info.write_regs and 'BF' in info.asmregs[0]:
+            crf = 'BF'
+        regnum, is_vec = yield from get_pdecode_cr_out(self.dec2, crf)
         crtest = self.crl[regnum]
         ffirst_hit = crtest[cr_bit] != ff_inv
-        log("cr test", regnum, int(crtest), crtest, cr_bit, ff_inv)
+        log("cr test", crf, regnum, int(crtest), crtest, cr_bit, ff_inv)
         log("cr test?", ffirst_hit)
         if not ffirst_hit:
             return False

diff --git a/src/openpower/decoder/isa/test_caller_svp64_inssort.py b/src/openpower/decoder/isa/test_caller_svp64_inssort.py
index 8e7cce4f8fda9552dc0b45a2b19cd5ce65c5f567..9703cebbe1af2b6d7e032b7c8b37246ac36b555d 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_inssort.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_inssort.py
@@ -67,25 +67,21 @@ class DecoderTestCase(FHDLTestCase):
                 assert crf == crs_expected[i]
 
     def tst_sv_insert_sort(self):
-        """>>> lst = ["svshape 7, 0, 0, 7, 0",
-                        "svremap 31, 0, 1, 0, 0, 0, 0",
-                       "sv.add *0, *8, *16"
-                        ]
-                REMAP add RT,RA,RB
-    ctr = alen-1
-    li r10, 1 # prepare mask
-    sld r10, alen, r10
-    addi r10, r10, -1 # all 1s. must be better way
-loop:
-    setvl r3, ctr
-    sv.mv/m=1<<r3 key, *array   # get key item
-    sld r10, 1  # shift in another zero MSB
-    sv.cmp/ff=GT/m=~r10 *0, *array, key # stop cmp at 1st GT fail
-    sv.mv/m=GT *array-1, *array    # after cmp and ffirst
-    getvl r3
-    sub r3, 1                   # reduce by one
-    sv.mv/m=1<<r3 *array, key   # put key into array
-    bc 16, loop                 # dec CTR, back around
+        """
+                ctr = alen-1
+                li r10, 1 # prepare mask
+                sld r10, alen, r10
+                addi r10, r10, -1 # all 1s. must be better way
+            loop:
+                setvl r3, ctr
+                sv.mv/m=1<<r3 key, *array   # get key item
+                sld r10, 1  # shift in another zero MSB
+                sv.cmp/ff=GT/m=~r10 *0, *array, key # stop cmp at 1st GT fail
+                sv.mv/m=GT *array-1, *array    # after cmp and ffirst
+                getvl r3
+                sub r3, 1                   # reduce by one
+                sv.mv/m=1<<r3 *array, key   # put key into array
+                bc 16, loop                 # dec CTR, back around
 
         """
         lst = SVP64Asm(["addi 10, 0, 1",
@@ -95,13 +91,16 @@ loop:
                         "mtspr 9, 11",
                         "setvl 3, 0, 10, 0, 1, 1",
                         "addi 3, 3, -1",
-                        "sv.addi/m=1<<r3 12, *16, 0",
-                        "sv.cmp/ff=gt/m=~r10 0, 1, *16, 0",
+                        "sv.addi/m=1<<r3 12, *16, 0",  # VEXTRACT to 12
+                        "sv.cmp/ff=le/m=~r10 *0, 1, *16, 12",
+                        "slw 10, 10, 9",
+                        "bc 16, 0, -28",  # decrement CTR, repeat
                         ])
         lst = list(lst)
 
         gprs = [0] * 64
-        vec = [1, 2, 3, 4, 9, 5, 6]
+        #vec = [1, 2, 3, 4, 9, 5, 6]
+        vec = [9, 5, 6]
 
         res = []
         # store GPRs