LLVMTargetRef target = ac_get_llvm_target(triple);
snprintf(features, sizeof(features),
- "+DumpCode,+vgpr-spilling,-fp32-denormals%s",
- family >= CHIP_VEGA10 ? ",+xnack" : ",-xnack");
+ "+DumpCode,+vgpr-spilling,-fp32-denormals%s%s",
+ family >= CHIP_VEGA10 ? ",+xnack" : ",-xnack",
+ tm_options & AC_TM_SISCHED ? ",+si-scheduler" : "");
LLVMTargetMachineRef tm = LLVMCreateTargetMachine(
target,
enum ac_target_machine_options {
AC_TM_SUPPORTS_SPILL = (1 << 0),
+ AC_TM_SISCHED = (1 << 1),
};
LLVMTargetMachineRef ac_create_target_machine(enum radeon_family family, enum ac_target_machine_options tm_options);
enum {
RADV_PERFTEST_BATCHCHAIN = 0x1,
+ RADV_PERFTEST_SISCHED = 0x2,
};
#endif
static const struct debug_control radv_perftest_options[] = {
{"batchchain", RADV_PERFTEST_BATCHCHAIN},
+ {"sisched", RADV_PERFTEST_SISCHED},
{NULL, 0}
};
options.supports_spill = device->llvm_supports_spill;
if (options.supports_spill)
tm_options |= AC_TM_SUPPORTS_SPILL;
+ if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
+ tm_options |= AC_TM_SISCHED;
tm = ac_create_target_machine(chip_family, tm_options);
ac_compile_nir_shader(tm, &binary, &variant->config,
&variant->info, shader, &options, dump);
options.chip_class = pipeline->device->physical_device->rad_info.chip_class;
if (options.supports_spill)
tm_options |= AC_TM_SUPPORTS_SPILL;
+ if (pipeline->device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
+ tm_options |= AC_TM_SISCHED;
tm = ac_create_target_machine(chip_family, tm_options);
ac_create_gs_copy_shader(tm, nir, &binary, &variant->config, &variant->info, &options, dump_shader);
LLVMDisposeTargetMachine(tm);