fprintf(f, " (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_NAME(cell->type),
lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : "");
for (auto &p : cell->parameters)
- if (p.second.bits.size() <= 32 && RTLIL::SigSpec(p.second).is_fully_def())
+ if (!p.second.str.empty())
+ fprintf(f, "\n (property %s (string \"%s\"))", EDIF_NAME(p.first), p.second.str.c_str());
+ else if (p.second.bits.size() <= 32 && RTLIL::SigSpec(p.second).is_fully_def())
fprintf(f, "\n (property %s (integer %u))", EDIF_NAME(p.first), p.second.as_int());
- else
- fprintf(f, "\n (property %s FIXME)", EDIF_NAME(p.first));
+ else {
+ std::string hex_string = "";
+ for (size_t i = 0; i < p.second.bits.size(); i += 4) {
+ int digit_value = 0;
+ if (i+0 < p.second.bits.size() && p.second.bits.at(i+0) == RTLIL::State::S1) digit_value += 1;
+ if (i+1 < p.second.bits.size() && p.second.bits.at(i+1) == RTLIL::State::S1) digit_value += 2;
+ if (i+2 < p.second.bits.size() && p.second.bits.at(i+2) == RTLIL::State::S1) digit_value += 3;
+ if (i+3 < p.second.bits.size() && p.second.bits.at(i+3) == RTLIL::State::S1) digit_value += 4;
+ char digit_str[2] = { "0123456789abcdef"[digit_value], 0 };
+ hex_string = std::string(digit_str) + hex_string;
+ }
+ fprintf(f, "\n (property %s (string \"%s\"))", EDIF_NAME(p.first), hex_string.c_str());
+ }
fprintf(f, ")\n");
for (auto &p : cell->connections) {
RTLIL::SigSpec sig = sigmap(p.second);