i965: Don't depth test the fake depthbuffer when one isn't present.

For the non-separate-stencil-only case, we've been using a NULL
surface for depth, so we didn't have to care.  However, to support
separate stencil with no depthbuffer, we have to make the depth
surface non-NULL or the stencil test always fails thanks to separate
stencil inheriting the surface type of depth.

Fixes hiz-depth-stencil-test-d0-s8.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>

diff --git a/src/mesa/drivers/dri/i965/gen6_depthstencil.c b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
index eec1bf690150f0a653d72cdebebd0ae3f01a9a02..c601a8fb13e29fc2ee2c6d7847431b2fee31e3fe 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_depthstencil.c
+++ b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
@@ -25,6 +25,7 @@
  *
  */
 
+#include "intel_fbo.h"
 #include "brw_context.h"
 #include "brw_state.h"
 
@@ -33,6 +34,10 @@ gen6_upload_depth_stencil_state(struct brw_context *brw)
 {
    struct gl_context *ctx = &brw->intel.ctx;
    struct gen6_depth_stencil_state *ds;
+   struct intel_renderbuffer *depth_irb;
+
+   /* _NEW_BUFFERS */
+   depth_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
 
    ds = brw_state_batch(brw, AUB_TRACE_DEPTH_STENCIL_STATE,
                        sizeof(*ds), 64,
@@ -77,7 +82,7 @@ gen6_upload_depth_stencil_state(struct brw_context *brw)
    }
 
    /* _NEW_DEPTH */
-   if (ctx->Depth.Test || brw->hiz.op) {
+   if ((ctx->Depth.Test || brw->hiz.op) && depth_irb) {
       assert(brw->hiz.op != BRW_HIZ_OP_DEPTH_RESOLVE || ctx->Depth.Test);
       assert(brw->hiz.op != BRW_HIZ_OP_HIZ_RESOLVE   || !ctx->Depth.Test);
       assert(brw->hiz.op != BRW_HIZ_OP_DEPTH_CLEAR   || !ctx->Depth.Test);