ac/gpu_info: add si_TA_CS_BC_BASE_ADDR_allowed

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index e2e41f0f47ad4dbb61834d7605abb48b6a93a77a..6f2fea895be3179b417e06ba6dad545a94f3fc3f 100644 (file)
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -318,6 +318,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
                                  !info->has_dedicated_vram;
        info->kernel_flushes_hdp_before_ib = true;
        info->htile_cmask_support_1d_tiling = true;
+       info->si_TA_CS_BC_BASE_ADDR_allowed = true;
 
        info->num_render_backends = amdinfo->rb_pipes;
        /* The value returned by the kernel driver was wrong. */
@@ -467,6 +468,7 @@ void ac_print_gpu_info(struct radeon_info *info)
        printf("    has_local_buffers = %u\n", info->has_local_buffers);
        printf("    kernel_flushes_hdp_before_ib = %u\n", info->kernel_flushes_hdp_before_ib);
        printf("    htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling);
+       printf("    si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed);
 
        printf("Shader core info:\n");
        printf("    max_shader_clock = %i\n", info->max_shader_clock);

diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 578c3fb7da166b60a790052ae4344a6eafb6792d..bc6350b5625110d21c4824d87fb88719141e4a7c 100644 (file)
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -98,6 +98,7 @@ struct radeon_info {
        bool                        has_local_buffers;
        bool                        kernel_flushes_hdp_before_ib;
        bool                        htile_cmask_support_1d_tiling;
+       bool                        si_TA_CS_BC_BASE_ADDR_allowed;
 
        /* Shader cores. */
        uint32_t                    r600_max_quad_pipes; /* wave size / 16 */

diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index e95e79c7b467df179debf59dd22843f14d192624..e20bae0afc4e7b11c615b47268fa2df75645b29f 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -331,9 +331,7 @@ static void si_initialize_compute(struct si_context *sctx)
                radeon_emit(cs, bc_va >> 8);  /* R_030E00_TA_CS_BC_BASE_ADDR */
                radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
        } else {
-               if (sctx->screen->info.drm_major == 3 ||
-                   (sctx->screen->info.drm_major == 2 &&
-                    sctx->screen->info.drm_minor >= 48)) {
+               if (sctx->screen->info.si_TA_CS_BC_BASE_ADDR_allowed) {
                        radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR,
                                              bc_va >> 8);
                }

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 21579fd9563d4c535a26e757e9f6df1f278f4eae..6040134c2da0b27f5f2fc9c090939b634ecc9c14 100644 (file)
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -532,6 +532,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
     /* HTILE is broken with 1D tiling on old kernels and CIK. */
     ws->info.htile_cmask_support_1d_tiling = ws->info.chip_class != CIK ||
                                              ws->info.drm_minor >= 38;
+    ws->info.si_TA_CS_BC_BASE_ADDR_allowed = ws->info.drm_minor >= 48;
 
     ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;