--- /dev/null
+CHIPSET(0x3577, I830_M, i8xx)
+CHIPSET(0x2562, 845_G, i8xx)
+CHIPSET(0x3582, I855_GM, i8xx)
+CHIPSET(0x2572, I865_G, i8xx)
+CHIPSET(0x2582, I915_G, i915)
+CHIPSET(0x258A, E7221_G, i915)
+CHIPSET(0x2592, I915_GM, i915)
+CHIPSET(0x2772, I945_G, i945)
+CHIPSET(0x27A2, I945_GM, i945)
+CHIPSET(0x27AE, I945_GME, i945)
+CHIPSET(0x29B2, Q35_G, i945)
+CHIPSET(0x29C2, G33_G, i945)
+CHIPSET(0x29D2, Q33_G, i945)
+CHIPSET(0xA011, IGD_GM, i945)
+CHIPSET(0xA001, IGD_G, i945)
--- /dev/null
+CHIPSET(0x29A2, I965_G, i965)
+CHIPSET(0x2992, I965_Q, i965)
+CHIPSET(0x2982, I965_G_1, i965)
+CHIPSET(0x2972, I946_GZ, i965)
+CHIPSET(0x2A02, I965_GM, i965)
+CHIPSET(0x2A12, I965_GME, i965)
+CHIPSET(0x2A42, GM45_GM, g4x)
+CHIPSET(0x2E02, IGD_E_G, g4x)
+CHIPSET(0x2E12, Q45_G, g4x)
+CHIPSET(0x2E22, G45_G, g4x)
+CHIPSET(0x2E32, G41_G, g4x)
+CHIPSET(0x2E42, B43_G, g4x)
+CHIPSET(0x2E92, B43_G1, g4x)
+CHIPSET(0x0042, ILD_G, ilk)
+CHIPSET(0x0046, ILM_G, ilk)
+CHIPSET(0x0102, SANDYBRIDGE_GT1, snb_gt1)
+CHIPSET(0x0112, SANDYBRIDGE_GT2, snb_gt2)
+CHIPSET(0x0122, SANDYBRIDGE_GT2_PLUS, snb_gt2)
+CHIPSET(0x0106, SANDYBRIDGE_M_GT1, snb_gt1)
+CHIPSET(0x0116, SANDYBRIDGE_M_GT2, snb_gt2)
+CHIPSET(0x0126, SANDYBRIDGE_M_GT2_PLUS, snb_gt2)
+CHIPSET(0x010A, SANDYBRIDGE_S, snb_gt1)
+CHIPSET(0x0152, IVYBRIDGE_GT1, ivb_gt1)
+CHIPSET(0x0162, IVYBRIDGE_GT2, ivb_gt2)
+CHIPSET(0x0156, IVYBRIDGE_M_GT1, ivb_gt1)
+CHIPSET(0x0166, IVYBRIDGE_M_GT2, ivb_gt2)
+CHIPSET(0x015a, IVYBRIDGE_S_GT1, ivb_gt1)