include:

	* opcode/arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
	Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
	and ARM_ARCH_V6ZKT2.
opcodes:
	* arm-dis.c (arm_opcodes): Document %E and %V.
	Add entries for v6T2 ARM instructions:
	bfc bfi mls strht ldrht ldrsht ldrsbt movw movt rbit ubfx sbfx.
	(print_insn_arm): Add support for %E and %V.

diff --git a/include/ChangeLog b/include/ChangeLog
index b659971c1107c295c79599f11d721d3b7b2c78f0..9dee8dd2a79e45c9e54aa5276f47853664f6a57c 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,9 @@
+2005-03-12  Zack Weinberg  <zack@codesourcery.com>
+
+       * opcode/arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
+       Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
+       and ARM_ARCH_V6ZKT2.
+
 2005-03-09  Mark Mitchell  <mark@codesourcery.com>
 
        * libiberty.h (gettimeofday): Declare.
@@ -58,7 +64,7 @@
        * dis-asm.h: Add prototype for print_insn_maxq_little.
 
 2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
-       
+
        * opcode/crx.h (enum argtype): Rename types, remove unused types.
 
 2004-10-27  Richard Earnshaw  <rearnsha@arm.com>
@@ -71,7 +77,7 @@
        (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
        (enum operand_type): Rearrange operands, edit comments.
        replace us<N> with ui<N> for unsigned immediate.
-       replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped 
+       replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
        displacements (respectively).
        replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
        (instruction type): Add NO_TYPE_INS.

diff --git a/include/opcode/arm.h b/include/opcode/arm.h
index dd90e2ac6694a816e50cd637dd4370f86c4e50d7..db3666591e5fce5b806914cabd62932cb8578816 100644 (file)
--- a/include/opcode/arm.h
+++ b/include/opcode/arm.h
@@ -25,15 +25,16 @@
 #define ARM_EXT_V3      0x00000008     /* MSR MRS.                */
 #define ARM_EXT_V3M     0x00000010     /* Allow long multiplies.  */
 #define ARM_EXT_V4      0x00000020     /* Allow half word loads.  */
-#define ARM_EXT_V4T     0x00000040     /* Thumb v1.               */
+#define ARM_EXT_V4T     0x00000040     /* Thumb.                  */
 #define ARM_EXT_V5      0x00000080     /* Allow CLZ, etc.         */
-#define ARM_EXT_V5T     0x00000100     /* Thumb v2.               */
+#define ARM_EXT_V5T     0x00000100     /* Improved interworking.  */
 #define ARM_EXT_V5ExP   0x00000200     /* DSP core set.           */
 #define ARM_EXT_V5E     0x00000400     /* DSP Double transfers.   */
 #define ARM_EXT_V5J     0x00000800     /* Jazelle extension.      */
 #define ARM_EXT_V6       0x00001000     /* ARM V6.                 */
 #define ARM_EXT_V6K      0x00002000     /* ARM V6K.                */
 #define ARM_EXT_V6Z      0x00004000     /* ARM V6Z.                */
+#define ARM_EXT_V6T2    0x00008000     /* Thumb-2.                */
 
 /* Co-processor space extensions.  */
 #define ARM_CEXT_XSCALE   0x00800000   /* Allow MIA etc.          */
@@ -65,6 +66,10 @@
 #define ARM_ARCH_V6K    (ARM_ARCH_V6    | ARM_EXT_V6K)
 #define ARM_ARCH_V6Z    (ARM_ARCH_V6    | ARM_EXT_V6Z)
 #define ARM_ARCH_V6ZK   (ARM_ARCH_V6    | ARM_EXT_V6K | ARM_EXT_V6Z)
+#define ARM_ARCH_V6T2   (ARM_ARCH_V6    | ARM_EXT_V6T2)
+#define ARM_ARCH_V6KT2  (ARM_ARCH_V6    | ARM_EXT_V6T2 | ARM_EXT_V6K)
+#define ARM_ARCH_V6ZT2  (ARM_ARCH_V6    | ARM_EXT_V6T2 | ARM_EXT_V6Z)
+#define ARM_ARCH_V6ZKT2 (ARM_ARCH_V6    | ARM_EXT_V6T2 | ARM_EXT_V6K | ARM_EXT_V6Z)
 
 /* Processors with specific extensions in the co-processor space.  */
 #define ARM_ARCH_XSCALE        (ARM_ARCH_V5TE  | ARM_CEXT_XSCALE)

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 7e3bbf55823d6a14c4dab70de94aa5117940afa5..883c7a954a4b6fd6948bd923e018273efa17d86f 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2005-03-12  Zack Weinberg  <zack@codesourcery.com>
+
+       * arm-dis.c (arm_opcodes): Document %E and %V.
+       Add entries for v6T2 ARM instructions:
+       bfc bfi mls strht ldrht ldrsht ldrsbt movw movt rbit ubfx sbfx.
+       (print_insn_arm): Add support for %E and %V.
+
 2005-03-10  Jeff Baker  <jbaker@qnx.com>
            Alan Modra  <amodra@bigpond.net.au>
 
@@ -5,7 +12,7 @@
        (powerpc_operands <SPRG>): Call the above.  Bit field is 5 bits.
        (SPRG_MASK): Delete.
        (XSPRG_MASK): Mask off extra bits now part of sprg field.
-        (powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask.  Move
+       (powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask.  Move
        mfsprg4..7 after msprg and consolidate.
 
 2005-03-09  Jan-Benedict Glaw  <jbglaw@lug-owl.de>

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 5388bd1c3d272d49361d49d0ff5a7258c5a93ec2..a87bcc0b2f839f56041c663c3ab26891edcac537 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -81,6 +81,8 @@
    %m                  print register mask for ldm/stm instruction
    %C                  print the PSR sub type.
    %F                  print the COUNT field of a LFM/SFM instruction.
+   %E                  print the LSB and WIDTH fields of a BFI or BFC instruction.
+   %V                   print the 16-bit immediate field of a MOVT or MOVW instruction.
 IWMMXT specific format options:
    %<bitfield>g         print as an iWMMXt 64-bit register
    %<bitfield>G         print as an iWMMXt general purpose or control register
@@ -118,6 +120,17 @@ static const struct arm_opcode arm_opcodes[] =
   {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
   {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
 
+  /* ARM V6T2 instructions.  */
+  {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15r, %E"},
+  {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15r, %0-3r, %E"},
+  {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
+  {ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "str%cht\t%12-15r, %s"},
+  {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%c%6's%5?hbt\t%12-15r, %s"},
+  {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15r, %V"},
+  {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15r, %V"},
+  {ARM_EXT_V6T2, 0x03ff0f30, 0x0fff0ff0, "rbit%c\t%12-15r, %0-3r"},
+  {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
+
   /* ARM V6Z instructions.  */
   {ARM_EXT_V6Z, 0x01600070, 0x0ff000f0, "smi%c\t%e"},
 
@@ -622,6 +635,13 @@ static const struct thumb_opcode thumb_opcodes[] =
 {
   /* Thumb instructions.  */
 
+  /* ARM V6K no-argument instructions.  */
+  {ARM_EXT_V6K, 0xbf00, 0xffff, "nop"},
+  {ARM_EXT_V6K, 0xbf10, 0xffff, "yield"},
+  {ARM_EXT_V6K, 0xbf20, 0xffff, "wfe"},
+  {ARM_EXT_V6K, 0xbf30, 0xffff, "wfi"},
+  {ARM_EXT_V6K, 0xbf40, 0xffff, "sev"},
+
   /* ARM V6.  */
   {ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f"},
   {ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f"},
@@ -929,7 +949,13 @@ print_insn_arm (pc, info, given)
          && info->mach != bfd_mach_arm_iWMMXt)
        insn = insn + IWMMXT_INSN_COUNT;
 
-      if ((given & insn->mask) == insn->value)
+      if ((given & insn->mask) == insn->value
+         /* Special case: an instruction with all bits set in the condition field
+            (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
+            or by the catchall at the end of the table.  */
+         && ((given & 0xF0000000) != 0xF0000000
+             || (insn->mask & 0xF0000000) == 0xF0000000
+             || (insn->mask == 0 && insn->value == 0)))
        {
          char * c;
 
@@ -1613,6 +1639,32 @@ print_insn_arm (pc, info, given)
                        }
                        break;
 
+                     case 'E':
+                       /* LSB and WIDTH fields of BFI or BFC.  The machine-
+                          language instruction encodes LSB and MSB.  */
+                       {
+                         long msb = (given & 0x001f0000) >> 16;
+                         long lsb = (given & 0x00000f80) >> 7;
+
+                         long width = msb - lsb + 1;
+                         if (width > 0)
+                           func (stream, "#%lu, #%lu", lsb, width);
+                         else
+                           func (stream, "(invalid: %lu:%lu)", lsb, msb);
+                       }
+                       break;
+
+                     case 'V':
+                       /* 16-bit unsigned immediate from a MOVT or MOVW
+                          instruction, encoded in bits 0:11 and 15:19.  */
+                       {
+                         long hi = (given & 0x000f0000) >> 4;
+                         long lo = (given & 0x00000fff);
+                         long imm16 = hi | lo;
+                         func (stream, "#%lu\t; 0x%lx", imm16, imm16);
+                       }
+                       break;
+
                      default:
                        abort ();
                      }