(no commit message)

diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn
index a435b12f4c8a109293cf3f284d2d688c44412b3d..c908420a8ea300a2060323d161f35e842f23ced8 100644 (file)
--- a/openpower/sv/biginteger/analysis.mdwn
+++ b/openpower/sv/biginteger/analysis.mdwn
@@ -284,7 +284,7 @@ detect*).
 SVP64 has the means to mark registers as scalar or vector. However
 the available space in the prefix is extremely limited (9 bits).
 With effectively 5 operands (3 in, 2 out) some compromises are needed.
-A little though gives a useful workaround: two modes,
+A little thought gives a useful workaround: two modes,
 controlled by a single bit in `RM.EXTRA`, determine whether the 5th
 register is set to RC or whether to RT+VL. This then leaves only
 4 registers to qualify as scalar/vector, which can use four