i965: Always set tiling for depth buffer on sandybridge

Sandybridge only support tiling depth buffer, always set tiling bit.

Fix 'fbo_firecube' demo.

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 6eeaba777207d35fd4d96e28ba9537c1eca1ae2c..7a334126f2bebcdc8ed872425164ee4020da023e 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -289,7 +289,7 @@ static void emit_depthbuffer(struct brw_context *brw)
       OUT_BATCH(((region->pitch * region->cpp) - 1) |
                (format << 18) |
                (BRW_TILEWALK_YMAJOR << 26) |
-               ((region->tiling != I915_TILING_NONE) << 27) |
+               (1 << 27) |
                (BRW_SURFACE_2D << 29));
       OUT_RELOC(region->buffer,
                I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,