configs: More fixes for the memory system updates

diff --git a/configs/example/fs.py b/configs/example/fs.py
index 4456212c9ef4d8dec311756ec137f40523f97563..cf3dfdb89dee57a2920675d9b9179865b7162bba 100644 (file)
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -193,6 +193,10 @@ if len(bm) == 2:
         drive_sys.cpu.physmem_port = drive_sys.physmem.port
     if options.kernel is not None:
         drive_sys.kernel = binary(options.kernel)
+    drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
+                               ranges = [AddrRange(bm[1].mem())])
+    drive_sys.iobridge.slave = drive_sys.iobus.port
+    drive_sys.iobridge.master = drive_sys.membus.port
 
     drive_sys.init_param = options.init_param
     root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)

diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index dc2219cd1ec763bdbd6578046e5ffdf39838f52f..3da47399e101773562cad5b6d0b414247a273750 100644 (file)
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -351,10 +351,11 @@ class VExpress_ELT(RealView):
     def attachOnChipIO(self, bus, bridge):
        self.gic.pio = bus.port
        self.a9scu.pio = bus.port
+       self.local_cpu_timer.pio = bus.port
        # Bridge ranges based on excluding what is part of on-chip I/O
        # (gic, a9scu)
        bridge.ranges = [AddrRange(self.pci_cfg_base, self.a9scu.pio_addr - 1),
-                        AddrRange(self.local_cpu_timer.pio_addr, Addr.max)]
+                        AddrRange(self.l2x0_fake.pio_addr, Addr.max)]
 
     # Attach I/O devices to specified bus object.  Can't do this
     # earlier, since the bus object itself is typically defined at the
@@ -363,7 +364,6 @@ class VExpress_ELT(RealView):
        self.elba_uart.pio       = bus.port
        self.uart.pio            = bus.port
        self.realview_io.pio     = bus.port
-       self.local_cpu_timer.pio = bus.port
        self.v2m_timer0.pio      = bus.port
        self.v2m_timer1.pio      = bus.port
        self.elba_timer0.pio     = bus.port