unsigned level = state->cbufs[0]->level;
unsigned pitch, slice;
unsigned color_info;
- unsigned format, swap;
+ unsigned format, swap, ntype;
int r;
+ const struct util_format_description *desc;
r = radeon_state_init(rstate, rscreen->rw, R600_CB0_TYPE, R600_CB0);
if (r)
pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[0]->height / 64 - 1;
+ ntype = 0;
+ desc = util_format_description(rtex->resource.base.b.format);
+ if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
+ ntype = NUM_FORMAT_SRGB;
+
format = r600_translate_colorformat(rtex->resource.base.b.format);
swap = r600_translate_colorswap(rtex->resource.base.b.format);
+
color_info = S_0280A0_FORMAT(format) |
- S_0280A0_COMP_SWAP(swap) |
- S_0280A0_BLEND_CLAMP(1) |
- S_0280A0_SOURCE_FORMAT(1);
+ S_0280A0_COMP_SWAP(swap) |
+ S_0280A0_BLEND_CLAMP(1) |
+ S_0280A0_SOURCE_FORMAT(1) |
+ S_0280A0_NUMBER_TYPE(ntype);
rstate->states[R600_CB0__CB_COLOR0_BASE] = 0x00000000;
rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
S_038010_DST_SEL_Y(r600_tex_swizzle(view->swizzle_g)) |
S_038010_DST_SEL_Z(r600_tex_swizzle(view->swizzle_r)) |
S_038010_DST_SEL_W(r600_tex_swizzle(view->swizzle_a)) |
+ S_038010_FORCE_DEGAMMA(desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB ? 1 : 0) |
S_038010_BASE_LEVEL(view->first_level);
rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
S_038014_LAST_LEVEL(view->last_level) |
case PIPE_FORMAT_B4G4R4X4_UNORM:
return SWAP_ALT;
/* 32-bit buffers. */
+
+ case PIPE_FORMAT_A8B8G8R8_SRGB:
+ return SWAP_STD_REV;
+ case PIPE_FORMAT_B8G8R8A8_SRGB:
+ return SWAP_ALT;
+
case PIPE_FORMAT_B8G8R8A8_UNORM:
case PIPE_FORMAT_B8G8R8X8_UNORM:
return SWAP_ALT;
case PIPE_FORMAT_X8B8G8R8_UNORM:
case PIPE_FORMAT_R8G8B8X8_UNORM:
case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
+ case PIPE_FORMAT_A8B8G8R8_SRGB:
+ case PIPE_FORMAT_B8G8R8A8_SRGB:
return V_0280A0_COLOR_8_8_8_8;
case PIPE_FORMAT_R10G10B10A2_UNORM: