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diff --git a/openpower/sv/remap.mdwn b/openpower/sv/remap.mdwn
index 9aa4c130c2e2856cd09c57680ee04210dfe591be..c65f41b95f97af47d741bc9e9a4373a8e0641bfd 100644 (file)
--- a/openpower/sv/remap.mdwn
+++ b/openpower/sv/remap.mdwn
@@ -37,9 +37,12 @@ Vector ISAs which would typically only have a limited set of instructions
 that can be structure-packed (LD/ST typically), REMAP may be applied to
 literally any instruction: CRs, Arithmetic, Logical, LD/ST, anything.
 
-Note that REMAP does not *directly* apply to sub-vector elements: that 
-is what swizzle is for.  Swizzle *can* however be applied to the same
-instruction as REMAP.  As explained in [[sv/mv.swizzle]], [[sv/mv.vec]] and the [[svp64/appendix]], Pack and Unpack EXTRA Mode bits
+When SUBVL is greater than 1 the group of Subvector
+elements are kept together, effectively the group becomes the
+element, and the group is REMAPed together.
+Swizzle *can* however be applied to the same
+instruction as REMAP, providing re-sequencing of
+Subvector elements that REMAP cannot. Also as explained in [[sv/mv.swizzle]], [[sv/mv.vec]] and the [[svp64/appendix]], Pack and Unpack EXTRA Mode bits
 can extend down into Sub-vector elements to perform vec2/vec3/vec4
 sequential reordering, but even here, REMAP is not extended down to
 the actual sub-vector elements themselves.