mem-ruby: Fix for Invalid transition in MOESI_CMP_directory
authoradarshpatil <adarshpatil123@gmail.com>
Wed, 27 May 2020 20:43:08 +0000 (21:43 +0100)
committerAdarsh Patil <adarshpatil123@gmail.com>
Fri, 29 May 2020 19:31:47 +0000 (19:31 +0000)
Send the correct sharer count from the memory directory to the requesting
L2 cache in data message reply.

Jira issue: https://gem5.atlassian.net/browse/GEM5-613

Change-Id: If76de630fd0001816e8836d9bf77961a94faaa7c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29552
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Reviewed-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm

index 3b09cbfa53e9b0a26746e74d8e5b6f395509bd5a..03010d53ac86b3ad447266a9f9811e3f8c69d027 100644 (file)
@@ -469,7 +469,11 @@ machine(MachineType:Directory, "Directory protocol")
         out_msg.Destination.add(in_msg.OriginalRequestorMachId);
         out_msg.DataBlk := in_msg.DataBlk;
         out_msg.Dirty := false; // By definition, the block is now clean
-        out_msg.Acks := in_msg.Acks;
+        if (getDirectoryEntry(in_msg.addr).Sharers.isElement(in_msg.OriginalRequestorMachId) == true) {
+         out_msg.Acks := (getDirectoryEntry(in_msg.addr).Sharers.count()) - 1;
+        } else {
+         out_msg.Acks := getDirectoryEntry(in_msg.addr).Sharers.count();
+        }
         if (in_msg.ReadX) {
           out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
         } else {